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The SystemVerilog class-body field regex in _augment_systemverilog_semantics matched only unqualified `<type> <name>;` declarations. Its `^\s*` prefix consumes leading whitespace but not leading class-property qualifiers, so a qualified field such as `rand Config m_cfg;` (three tokens) failed the two-token shape and its type reference was silently dropped from the graph. Consume optional leading qualifiers (rand/randc/local/protected/static/const/ automatic/var) before the type token. Zero qualifiers preserves the existing behavior; the type and name capture are unchanged. Adds test_systemverilog_qualified_field_references plus rand- and protected-qualified fields (and a Config class) to the shared .sv fixture.
45 lines
637 B
Systemverilog
45 lines
637 B
Systemverilog
package math_pkg;
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endpackage
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interface class Processor;
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endclass
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class BaseProcessor;
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endclass
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class Payload;
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endclass
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class Config;
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endclass
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class Result #(type T = Payload);
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T value;
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endclass
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class DataProcessor extends BaseProcessor implements Processor;
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Result #(Payload) current;
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rand Config m_cfg;
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protected BaseProcessor m_parent;
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function Result #(Payload) build(Payload input);
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return current;
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endfunction
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endclass
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module leaf;
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endmodule
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module top;
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import math_pkg::*;
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function int add(input int a, input int b);
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return a + b;
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endfunction
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task tick;
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endtask
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leaf u_leaf();
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endmodule
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