diff --git a/docs/credits_acknowledgements.rst b/docs/credits_acknowledgements.rst
index c0831e9a9..f23578f2a 100644
--- a/docs/credits_acknowledgements.rst
+++ b/docs/credits_acknowledgements.rst
@@ -124,6 +124,10 @@ The following libraries and components are incorporated into RenderDoc, listed h
Used to emit profiling events in development builds.
+* `AGS `_ - Copyright (c) 2020 Advanced Micro Devices, Inc. Distributed under the MIT License.
+
+ Used to intercept and test AGS calls on D3D11/D3D12.
+
Thanks
------
diff --git a/renderdoc/driver/ihv/amd/official/ags/amd_ags.h b/renderdoc/driver/ihv/amd/official/ags/amd_ags.h
index 4a0948a2b..f9c697b8d 100644
--- a/renderdoc/driver/ihv/amd/official/ags/amd_ags.h
+++ b/renderdoc/driver/ihv/amd/official/ags/amd_ags.h
@@ -106,7 +106,7 @@
#define AMD_AGS_VERSION_MAJOR 6 ///< AGS major version
#define AMD_AGS_VERSION_MINOR 0 ///< AGS minor version
-#define AMD_AGS_VERSION_PATCH 0 ///< AGS patch version
+#define AMD_AGS_VERSION_PATCH 1 ///< AGS patch version
#ifdef __cplusplus
extern "C" {
@@ -468,8 +468,8 @@ typedef struct AGSDX12ReturnedParams
unsigned int baseInstance : 1; ///< Supported in Radeon Software Version 20.2.1 onwards.
unsigned int getWaveSize : 1; ///< Supported in Radeon Software Version 20.5.1 onwards.
unsigned int floatConversion : 1; ///< Supported in Radeon Software Version 20.5.1 onwards.
- unsigned int readLaneAt : 1; ///< Supported in Radeon Software Version 20.11.1 onwards.
- unsigned int rayHitToken : 1; ///< Supported in Radeon Software Version 20.11.1 onwards.
+ unsigned int readLaneAt : 1; ///< Supported in Radeon Software Version 20.11.2 onwards.
+ unsigned int rayHitToken : 1; ///< Supported in Radeon Software Version 20.11.2 onwards.
unsigned int padding : 20; ///< Reserved
} ExtensionsSupported;
ExtensionsSupported extensionsSupported; ///< List of supported extensions
diff --git a/util/installer/LICENSE.rtf b/util/installer/LICENSE.rtf
index d466ec60a..24c3ee2d4 100644
--- a/util/installer/LICENSE.rtf
+++ b/util/installer/LICENSE.rtf
@@ -40,5 +40,6 @@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLI
{\field{\*\fldinst{HYPERLINK "{\pntext\f1\'B7\tab}http://download.nvidia.com/XFree86/nvapi-open-source-sdk/"}}{\fldrslt{\ul\cf1 http://download.nvidia.com/XFree86/nvapi-open-source-sdk}}}\f0\fs22\line nvapi open source SDK distributed under the MIT License. Copyright (c) 2019, NVIDIA CORPORATION.\par
{\field{\*\fldinst{HYPERLINK "{\pntext\f1\'B7\tab}http://half.sourceforge.net/"}}{\fldrslt{\ul\cf1 http://half.sourceforge.net/}}}\f0\fs22\line half.hpp distributed under the MIT License. Copyright (c) 2012-2019 Christian Rau.\par
{\field{\*\fldinst{HYPERLINK "{\pntext\f1\'B7\tab}https://superluminal.eu/"}}{\fldrslt{\ul\cf1 https://superluminal.eu/}}}\f0\fs22\line Superluminal distributed under the BSD License. Copyright (c) 2019-2020 Superluminal.\par
+{\field{\*\fldinst{HYPERLINK "{\pntext\f1\'B7\tab}https://github.com/GPUOpen-LibrariesAndSDKs/AGS_SDK/"}}{\fldrslt{\ul\cf1 https://github.com/GPUOpen-LibrariesAndSDKs/AGS_SDK/}}}\f0\fs22\line AGS distributed under the MIT License. Copyright (c) 2020 Advanced Micro Devices, Inc.\par
}
diff --git a/util/test/demos/3rdparty/ags/ags_shader_intrinsics_dx11.hlsl.h b/util/test/demos/3rdparty/ags/ags_shader_intrinsics_dx11.hlsl.h
index 0aa7c4e4a..68d834911 100644
--- a/util/test/demos/3rdparty/ags/ags_shader_intrinsics_dx11.hlsl.h
+++ b/util/test/demos/3rdparty/ags/ags_shader_intrinsics_dx11.hlsl.h
@@ -73,15 +73,15 @@ static const char *ags_shader_intrinsics_dx11_hlsl_array[] = {R"EOSHADER(
#define AmdDxExtShaderIntrinsicsOpcode_Max3F 0x0d
#define AmdDxExtShaderIntrinsicsOpcode_BaryCoord 0x0e
#define AmdDxExtShaderIntrinsicsOpcode_VtxParam 0x0f
-#define AmdDxExtShaderIntrinsicsOpCode_ViewportIndex 0x10
-#define AmdDxExtShaderIntrinsicsOpCode_RtArraySlice 0x11
-#define AmdDxExtShaderIntrinsicsOpCode_WaveReduce 0x12
-#define AmdDxExtShaderIntrinsicsOpCode_WaveScan 0x13
-#define AmdDxExtShaderIntrinsicsOpCode_Reserved1 0x14
-#define AmdDxExtShaderIntrinsicsOpCode_Reserved2 0x15
-#define AmdDxExtShaderIntrinsicsOpCode_Reserved3 0x16
-#define AmdDxExtShaderIntrinsicsOpCode_DrawIndex 0x17
-#define AmdDxExtShaderIntrinsicsOpCode_AtomicU64 0x18
+#define AmdDxExtShaderIntrinsicsOpcode_ViewportIndex 0x10
+#define AmdDxExtShaderIntrinsicsOpcode_RtArraySlice 0x11
+#define AmdDxExtShaderIntrinsicsOpcode_WaveReduce 0x12
+#define AmdDxExtShaderIntrinsicsOpcode_WaveScan 0x13
+#define AmdDxExtShaderIntrinsicsOpcode_Reserved1 0x14
+#define AmdDxExtShaderIntrinsicsOpcode_Reserved2 0x15
+#define AmdDxExtShaderIntrinsicsOpcode_Reserved3 0x16
+#define AmdDxExtShaderIntrinsicsOpcode_DrawIndex 0x17
+#define AmdDxExtShaderIntrinsicsOpcode_AtomicU64 0x18
#define AmdDxExtShaderIntrinsicsOpcode_GetWaveSize 0x19
#define AmdDxExtShaderIntrinsicsOpcode_BaseInstance 0x1a
#define AmdDxExtShaderIntrinsicsOpcode_BaseVertex 0x1b
@@ -867,7 +867,7 @@ float AmdDxExtShaderIntrinsics_VertexParameterComponent(uint vertexIdx, uint par
uint AmdDxExtShaderIntrinsics_GetViewportIndex()
{
uint retVal;
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_ViewportIndex, 0, 0);
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_ViewportIndex, 0, 0);
retVal = asuint(AmdDxExtShaderIntrinsicsResource.SampleLevel(AmdDxExtShaderIntrinsicsSamplerState,
float3(0, 0, 0),
@@ -891,7 +891,7 @@ uint AmdDxExtShaderIntrinsics_GetViewportIndex()
uint AmdDxExtShaderIntrinsics_GetViewportIndexPsOnly()
{
uint retVal;
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_ViewportIndex, 0, 0);
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_ViewportIndex, 0, 0);
AmdDxExtShaderIntrinsicsUAV.InterlockedCompareExchange(instruction, 0, 0, retVal);
@@ -914,7 +914,7 @@ uint AmdDxExtShaderIntrinsics_GetViewportIndexPsOnly()
uint AmdDxExtShaderIntrinsics_GetRTArraySlice()
{
uint retVal;
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_RtArraySlice, 0, 0);
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_RtArraySlice, 0, 0);
retVal = asuint(AmdDxExtShaderIntrinsicsResource.SampleLevel(AmdDxExtShaderIntrinsicsSamplerState,
float3(0, 0, 0),
@@ -938,7 +938,7 @@ uint AmdDxExtShaderIntrinsics_GetRTArraySlice()
uint AmdDxExtShaderIntrinsics_GetRTArraySlicePsOnly()
{
uint retVal;
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_RtArraySlice, 0, 0);
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_RtArraySlice, 0, 0);
AmdDxExtShaderIntrinsicsUAV.InterlockedCompareExchange(instruction, 0, 0, retVal);
@@ -965,7 +965,7 @@ uint AmdDxExtShaderIntrinsics_GetRTArraySlicePsOnly()
*/
float AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, float src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveReduce,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveReduce,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift));
uint retVal;
@@ -982,7 +982,7 @@ float AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, float src)
*/
float2 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, float2 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveReduce,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveReduce,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift));
uint2 retVal;
@@ -1002,7 +1002,7 @@ float2 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, float2 src)
*/
float3 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, float3 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveReduce,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveReduce,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift));
uint3 retVal;
@@ -1021,7 +1021,7 @@ float3 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, float3 src)
*/
float4 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, float4 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveReduce,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveReduce,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift));
uint4 retVal;
@@ -1041,7 +1041,7 @@ float4 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, float4 src)
*/
int AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, int src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveReduce,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveReduce,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift));
uint retVal;
@@ -1058,7 +1058,7 @@ int AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, int src)
*/
int2 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, int2 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveReduce,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveReduce,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift));
uint2 retVal;
@@ -1076,7 +1076,7 @@ int2 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, int2 src)
*/
int3 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, int3 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveReduce,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveReduce,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift));
uint3 retVal;
@@ -1095,7 +1095,7 @@ int3 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, int3 src)
*/
int4 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, int4 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveReduce,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveReduce,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift));
uint4 retVal;
@@ -1130,7 +1130,7 @@ int4 AmdDxExtShaderIntrinsics_WaveReduce(uint waveOp, int4 src)
*/
float AmdDxExtShaderIntrinsics_WaveScan(uint waveOp, uint flags, float src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveScan,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveScan,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift) |
(flags << AmdDxExtShaderIntrinsicsWaveOp_FlagShift));
@@ -1147,7 +1147,7 @@ float AmdDxExtShaderIntrinsics_WaveScan(uint waveOp, uint flags, float src)
*/
float2 AmdDxExtShaderIntrinsics_WaveScan(uint waveOp, uint flags, float2 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveScan,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveScan,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift) |
(flags << AmdDxExtShaderIntrinsicsWaveOp_FlagShift));
@@ -1165,7 +1165,7 @@ float2 AmdDxExtShaderIntrinsics_WaveScan(uint waveOp, uint flags, float2 src)
*/
float3 AmdDxExtShaderIntrinsics_WaveScan(uint waveOp, uint flags, float3 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveScan,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveScan,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift) |
(flags << AmdDxExtShaderIntrinsicsWaveOp_FlagShift));
@@ -1184,7 +1184,7 @@ float3 AmdDxExtShaderIntrinsics_WaveScan(uint waveOp, uint flags, float3 src)
*/
float4 AmdDxExtShaderIntrinsics_WaveScan(uint waveOp, uint flags, float4 src)
{
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_WaveScan,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_WaveScan,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
(waveOp << AmdDxExtShaderIntrinsicsWaveOp_OpcodeShift) |
(flags << AmdDxExtShaderIntrinsicsWaveOp_FlagShift));
@@ -1212,7 +1212,7 @@ float4 AmdDxExtShaderIntrinsics_WaveScan(uint waveOp, uint flags, float4 src)
uint AmdDxExtShaderIntrinsics_GetDrawIndex()
{
uint retVal;
- uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpCode_DrawIndex,
+ uint instruction = MakeAmdShaderIntrinsicsInstruction(AmdDxExtShaderIntrinsicsOpcode_DrawIndex,
AmdDxExtShaderIntrinsicsOpcodePhase_0,
0);
AmdDxExtShaderIntrinsicsUAV.InterlockedCompareExchange(instruction, 0, 0, retVal);
@@ -1280,13 +1280,13 @@ uint4 AmdDxExtShaderIntrinsics_MakeAtomicInstructions(uint op)
{
uint4 instructions;
instructions.x = MakeAmdShaderIntrinsicsInstruction(
- AmdDxExtShaderIntrinsicsOpCode_AtomicU64, AmdDxExtShaderIntrinsicsOpcodePhase_0, op);
+ AmdDxExtShaderIntrinsicsOpcode_AtomicU64, AmdDxExtShaderIntrinsicsOpcodePhase_0, op);
instructions.y = MakeAmdShaderIntrinsicsInstruction(
- AmdDxExtShaderIntrinsicsOpCode_AtomicU64, AmdDxExtShaderIntrinsicsOpcodePhase_1, op);
+ AmdDxExtShaderIntrinsicsOpcode_AtomicU64, AmdDxExtShaderIntrinsicsOpcodePhase_1, op);
instructions.z = MakeAmdShaderIntrinsicsInstruction(
- AmdDxExtShaderIntrinsicsOpCode_AtomicU64, AmdDxExtShaderIntrinsicsOpcodePhase_2, op);
+ AmdDxExtShaderIntrinsicsOpcode_AtomicU64, AmdDxExtShaderIntrinsicsOpcodePhase_2, op);
instructions.w = MakeAmdShaderIntrinsicsInstruction(
- AmdDxExtShaderIntrinsicsOpCode_AtomicU64, AmdDxExtShaderIntrinsicsOpcodePhase_3, op);
+ AmdDxExtShaderIntrinsicsOpcode_AtomicU64, AmdDxExtShaderIntrinsicsOpcodePhase_3, op);
return instructions;
}
@@ -1417,7 +1417,7 @@ uint2 AmdDxExtShaderIntrinsics_AtomicOp(
***********************************************************************************************************************
* AmdDxExtShaderIntrinsics_AtomicMinU64
*
-* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpCode_AtomicU64) returned S_OK.
+* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpcode_AtomicU64) returned S_OK.
*
* Performs 64-bit atomic minimum of value with the UAV at address, returns the original value.
*
@@ -1453,7 +1453,7 @@ uint2 AmdDxExtShaderIntrinsics_AtomicMinU64(RWTexture3D uav, uint3 addres
***********************************************************************************************************************
* AmdDxExtShaderIntrinsics_AtomicMaxU64
*
-* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpCode_AtomicU64) returned S_OK.
+* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpcode_AtomicU64) returned S_OK.
*
* Performs 64-bit atomic maximum of value with the UAV at address, returns the original value.
*
@@ -1489,7 +1489,7 @@ uint2 AmdDxExtShaderIntrinsics_AtomicMaxU64(RWTexture3D uav, uint3 addres
***********************************************************************************************************************
* AmdDxExtShaderIntrinsics_AtomicAndU64
*
-* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpCode_AtomicU64) returned S_OK.
+* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpcode_AtomicU64) returned S_OK.
*
* Performs 64-bit atomic AND of value with the UAV at address, returns the original value.
*
@@ -1525,7 +1525,7 @@ uint2 AmdDxExtShaderIntrinsics_AtomicAndU64(RWTexture3D uav, uint3 addres
***********************************************************************************************************************
* AmdDxExtShaderIntrinsics_AtomicOrU64
*
-* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpCode_AtomicU64) returned S_OK.
+* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpcode_AtomicU64) returned S_OK.
*
* Performs 64-bit atomic OR of value with the UAV at address, returns the original value.
*
@@ -1561,7 +1561,7 @@ uint2 AmdDxExtShaderIntrinsics_AtomicOrU64(RWTexture3D uav, uint3 address
***********************************************************************************************************************
* AmdDxExtShaderIntrinsics_AtomicXorU64
*
-* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpCode_AtomicU64) returned S_OK.
+* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpcode_AtomicU64) returned S_OK.
*
* Performs 64-bit atomic XOR of value with the UAV at address, returns the original value.
*
@@ -1599,7 +1599,7 @@ uint2 AmdDxExtShaderIntrinsics_AtomicXorU64(RWTexture3D uav, uint3 addres
***********************************************************************************************************************
* AmdDxExtShaderIntrinsics_AtomicAddU64
*
-* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpCode_AtomicU64) returned S_OK.
+* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpcode_AtomicU64) returned S_OK.
*
* Performs 64-bit atomic add of value with the UAV at address, returns the original value.
*
@@ -1635,7 +1635,7 @@ uint2 AmdDxExtShaderIntrinsics_AtomicAddU64(RWTexture3D uav, uint3 addres
***********************************************************************************************************************
* AmdDxExtShaderIntrinsics_AtomicXchgU64
*
-* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpCode_AtomicU64) returned S_OK.
+* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpcode_AtomicU64) returned S_OK.
*
* Performs 64-bit atomic exchange of value with the UAV at address, returns the original value.
*
@@ -1671,7 +1671,7 @@ uint2 AmdDxExtShaderIntrinsics_AtomicXchgU64(RWTexture3D uav, uint3 addre
***********************************************************************************************************************
* AmdDxExtShaderIntrinsics_AtomicCmpXchgU64
*
-* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpCode_AtomicU64) returned S_OK.
+* The following functions are available if CheckSupport(AmdDxExtShaderIntrinsicsOpcode_AtomicU64) returned S_OK.
*
* Performs 64-bit atomic compare of comparison value with UAV at address, stores value if values match,
* returns the original value.
diff --git a/util/test/demos/3rdparty/ags/ags_shader_intrinsics_dx12.hlsl.h b/util/test/demos/3rdparty/ags/ags_shader_intrinsics_dx12.hlsl.h
index 08f027040..3d2030711 100644
--- a/util/test/demos/3rdparty/ags/ags_shader_intrinsics_dx12.hlsl.h
+++ b/util/test/demos/3rdparty/ags/ags_shader_intrinsics_dx12.hlsl.h
@@ -306,6 +306,7 @@ float AmdExtD3DShaderIntrinsics_ReadfirstlaneF(float src)
return asfloat(retVal);
}
+
/**
***********************************************************************************************************************
* AmdExtD3DShaderIntrinsics_ReadfirstlaneU
@@ -2101,8 +2102,7 @@ int2 AmdExtD3DShaderIntrinsics_WaveActiveProduct(int2 src)
return AmdExtD3DShaderIntrinsics_WaveReduce(AmdExtD3DShaderIntrinsicsWaveOp_MulI, src);
}
-)EOSHADER",
- R"EOSHADER(
+)EOSHADER", R"EOSHADER(
/**
***********************************************************************************************************************
diff --git a/util/test/demos/3rdparty/ags/amd_ags.h b/util/test/demos/3rdparty/ags/amd_ags.h
index 4a0948a2b..f9c697b8d 100644
--- a/util/test/demos/3rdparty/ags/amd_ags.h
+++ b/util/test/demos/3rdparty/ags/amd_ags.h
@@ -106,7 +106,7 @@
#define AMD_AGS_VERSION_MAJOR 6 ///< AGS major version
#define AMD_AGS_VERSION_MINOR 0 ///< AGS minor version
-#define AMD_AGS_VERSION_PATCH 0 ///< AGS patch version
+#define AMD_AGS_VERSION_PATCH 1 ///< AGS patch version
#ifdef __cplusplus
extern "C" {
@@ -468,8 +468,8 @@ typedef struct AGSDX12ReturnedParams
unsigned int baseInstance : 1; ///< Supported in Radeon Software Version 20.2.1 onwards.
unsigned int getWaveSize : 1; ///< Supported in Radeon Software Version 20.5.1 onwards.
unsigned int floatConversion : 1; ///< Supported in Radeon Software Version 20.5.1 onwards.
- unsigned int readLaneAt : 1; ///< Supported in Radeon Software Version 20.11.1 onwards.
- unsigned int rayHitToken : 1; ///< Supported in Radeon Software Version 20.11.1 onwards.
+ unsigned int readLaneAt : 1; ///< Supported in Radeon Software Version 20.11.2 onwards.
+ unsigned int rayHitToken : 1; ///< Supported in Radeon Software Version 20.11.2 onwards.
unsigned int padding : 20; ///< Reserved
} ExtensionsSupported;
ExtensionsSupported extensionsSupported; ///< List of supported extensions