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Update SPIR-V files to latest

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baldurk
2026-07-03 14:19:33 +01:00
parent 9c7a4c956f
commit 2e351a8801
9 changed files with 1360 additions and 80 deletions
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renderdoc/driver/shaders/spirv/spir-v.xml
+12 -5
View File
@@ -82,7 +82,9 @@
<id value="47" vendor="ARM" comment="Contact Christopher Gautier, christopher.gautier@arm.com"/>
<id value="48" vendor="Goopax" comment="Contact Ingo Josopait, josopait@goopax.com"/>
<id value="49" vendor="Icyllis Milica" tool="Arc3D Shader Compiler" comment="Contact Icyllis Milica, https://github.com/BloCamLimb/Arc3D"/>
<unused start="50" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
<id value="50" vendor="Isochron" tool="Pred" comment="Contact Justin Ead, jebrim@isochrontechnologies.com"/>
<id value="51" vendor="apilatosba" tool="Apila Jai Compiler" comment="https://github.com/apilatosba/jai_to_spirv_compiler"/>
<unused start="52" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
</ids>
<!-- SECTION: SPIR-V Opcodes and Enumerants -->
@@ -178,13 +180,15 @@
<ids type="enumerant" start="6720" end="6783" vendor="MediaTek" comment="Contact samuel.huang@mediatek.com"/>
<ids type="enumerant" start="6784" end="6911" vendor="Intel" comment="Contact mariusz.merecki@intel.com"/>
<ids type="enumerant" start="6912" end="6975" vendor="Valve" comment="Contact michael.blumenkrantz@gmail.com"/>
<ids type="enumerant" start="6976" end="7039" vendor="Broadcom" comment="Contact gleese@broadcom.com"/>
<ids type="enumerant" start="7040" end="7103" vendor="Samsung" comment="Contact r.potter@samsung.com"/>
<!-- Enumerants to reserve for future use. To get a block, allocate
multiples of 64 starting at the lowest available point in this
block and add a corresponding <ids> tag immediately above. Make
sure to fill in the vendor attribute, and preferably add a contact
person/address in a comment attribute. -->
<!-- Example new block: <ids type="enumerant" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> -->
<ids type="enumerant" start="6976" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<ids type="enumerant" start="7104" end="4294967295" comment="Enumerant range reservable for future use by vendors"/>
<!-- End reservations of enumerants -->
@@ -205,7 +209,8 @@
<!-- Reserved loop control bits -->
<ids type="LoopControl" start="0" end="15" vendor="Khronos" comment="Reserved LoopControl bits, not available to vendors - see the SPIR-V Specification"/>
<ids type="LoopControl" start="16" end="27" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
<ids type="LoopControl" start="28" end="30" comment="Unreserved bits reservable for use by vendors"/>
<ids type="LoopControl" start="28" end="28" vendor="Qualcomm" comment="Contact wooykim@qti.qualcomm.com"/>
<ids type="LoopControl" start="29" end="30" comment="Unreserved bits reservable for use by vendors"/>
<ids type="LoopControl" start="31" end="31" vendor="Khronos" comment="Reserved LoopControl bit, not available to vendors"/>
@@ -246,7 +251,8 @@
<ids type="FPFastMathMode" start="0" end="15" vendor="Khronos" comment="Reserved FPFastMathMode bits, not available to vendors - see the SPIR-V Specification"/>
<ids type="FPFastMathMode" start="16" end="17" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
<ids type="FPFastMathMode" start="18" end="18" vendor="khronos" comment="Reserved FPFastMathMode bit, not available to vendors - see SPV_KHR_float_controls2"/>
<ids type="FPFastMathMode" start="19" end="31" comment="Unreserved bits reservable for use by vendors"/>
<ids type="FPFastMathMode" start="19" end="20" vendor="Broadcom" comment="Contact gleese@broadcom.com"/>
<ids type="FPFastMathMode" start="21" end="31" comment="Unreserved bits reservable for use by vendors"/>
<!-- SECTION: SPIR-V Memory Operand Bit Reservations -->
@@ -287,7 +293,8 @@
<!-- Reserved image operand bits -->
<ids type="ImageOperand" start="0" end="15" vendor="Khronos" comment="Reserved ImageOperand bits, not available to vendors - see the SPIR-V Specification"/>
<ids type="ImageOperand" start="16" end="16" vendor="Nvidia" comment="Contact pmistry@nvidia.com"/>
<ids type="ImageOperand" start="17" end="30" comment="Unreserved bits reservable for use by vendors"/>
<ids type="ImageOperand" start="17" end="17" vendor="Google" comment="Contact syoussefi@google.com"/>
<ids type="ImageOperand" start="18" end="30" comment="Unreserved bits reservable for use by vendors"/>
<ids type="ImageOperand" start="31" end="31" vendor="Khronos" comment="Reserved ImageOperand bit, not available to vendors"/>
</registry>
renderdoc/driver/shaders/spirv/spirv.core.grammar.json
+420 -18
View File
@@ -11,7 +11,7 @@
"magic_number" : "0x07230203",
"major_version" : 1,
"minor_version" : 6,
"revision" : 4,
"revision" : 7,
"instruction_printing_class" : [
{
"tag" : "@exclude"
@@ -4558,6 +4558,19 @@
"capabilities" : [ "GraphARM" ],
"version" : "None"
},
{
"opname" : "OpBitcastExtractEXT",
"class" : "Conversion",
"opcode" : 4195,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Base" },
{ "kind" : "IdRef", "name" : "Offset" }
],
"capabilities" : [ "BitcastExtractEXT" ],
"version" : "None"
},
{
"opname" : "OpTerminateInvocation",
"class" : "Control-Flow",
@@ -5408,6 +5421,22 @@
"capabilities" : [ "CooperativeMatrixConversionQCOM" ],
"version" : "None"
},
{
"opname" : "OpImageGatherQCOM",
"class" : "Image",
"opcode" : 4545,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Sampled Image" },
{ "kind" : "IdRef", "name" : "Coordinate" },
{ "kind" : "IdRef", "name" : "Component" },
{ "kind" : "IdRef", "name" : "Mode" },
{ "kind" : "ImageOperands", "quantifier" : "?" }
],
"capabilities" : [ "ImageGatherLinearQCOM", "ImageGatherExtendedModesQCOM" ],
"version" : "None"
},
{
"opname" : "OpGroupIAddNonUniformAMD",
"class" : "Group",
@@ -5718,6 +5747,17 @@
"capabilities": [ "DescriptorHeapEXT" ],
"version" : "None"
},
{
"opname" : "OpAbortKHR",
"class" : "Control-Flow",
"opcode" : 5121,
"operands" : [
{ "kind" : "IdRef", "name" : "Message Type" },
{ "kind" : "IdRef", "name" : "Message'" }
],
"capabilities" : [ "AbortKHR" ],
"version" : "None"
},
{
"opname" : "OpUntypedImageTexelPointerEXT",
"class" : "Memory",
@@ -5757,6 +5797,55 @@
"capabilities": [ "DescriptorHeapEXT" ],
"version" : "None"
},
{
"opname" : "OpConstantDataKHR",
"class" : "Constant-Creation",
"opcode" : 5147,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "LiteralInteger", "quantifier" : "*", "name" : "Data" }
],
"capabilities" : [ "ConstantDataKHR" ],
"version" : "None"
},
{
"opname" : "OpSpecConstantDataKHR",
"class" : "Constant-Creation",
"opcode" : 5148,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "LiteralInteger", "quantifier" : "*", "name" : "Data" }
],
"capabilities" : [ "ConstantDataKHR" ],
"version" : "None"
},
{
"opname" : "OpPoisonKHR",
"class" : "Miscellaneous",
"opcode" : 5158,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" }
],
"capabilities" : [ "PoisonFreezeKHR" ],
"provisional" : true,
"version" : "None"
},
{
"opname" : "OpFreezeKHR",
"class" : "Miscellaneous",
"opcode" : 5159,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Value" }
],
"capabilities" : [ "PoisonFreezeKHR" ],
"provisional" : true,
"version" : "None"
},
{
"opname" : "OpHitObjectRecordHitMotionNV",
"class" : "Reserved",
@@ -6445,7 +6534,8 @@
{ "kind" : "IdRef", "name" : "Hit Object" },
{ "kind" : "IdRef", "name" : "Ray Query" },
{ "kind" : "IdRef", "name" : "SBT Record Index" },
{ "kind" : "IdRef", "name" : "Hit Object Attributes" }
{ "kind" : "IdRef", "name" : "Hit Object Attributes" },
{ "kind" : "IdRef", "quantifier" : "?", "name" : "Hit Kind" }
],
"capabilities" : [ "ShaderInvocationReorderEXT" ],
"version" : "None"
@@ -10742,8 +10832,8 @@
"aliases" : [ "OpReadPipeBlockingINTEL" ],
"opcode" : 5946,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Pipe" },
{ "kind" : "IdRef", "name" : "Pointer" },
{ "kind" : "IdRef", "name" : "Packet Size" },
{ "kind" : "IdRef", "name" : "Packet Alignment" }
],
@@ -10756,8 +10846,8 @@
"aliases" : [ "OpWritePipeBlockingINTEL" ],
"opcode" : 5947,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Pipe" },
{ "kind" : "IdRef", "name" : "Pointer" },
{ "kind" : "IdRef", "name" : "Packet Size" },
{ "kind" : "IdRef", "name" : "Packet Alignment" }
],
@@ -11162,8 +11252,6 @@
"class" : "Composite",
"opcode" : 6096,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "quantifier" : "*", "name" : "Constituents" }
],
"capabilities" : [ "LongCompositesINTEL" ],
@@ -11194,27 +11282,29 @@
"version" : "None"
},
{
"opname" : "OpControlBarrierArriveINTEL",
"opname" : "OpControlBarrierArriveEXT",
"class" : "Barrier",
"aliases" : [ "OpControlBarrierArriveINTEL" ],
"opcode" : 6142,
"operands" : [
{ "kind" : "IdScope", "name" : "Execution" },
{ "kind" : "IdScope", "name" : "Memory" },
{ "kind" : "IdMemorySemantics", "name" : "Semantics" }
],
"capabilities" : [ "SplitBarrierINTEL" ],
"capabilities" : [ "SplitBarrierEXT" ],
"version" : "None"
},
{
"opname" : "OpControlBarrierWaitINTEL",
"opname" : "OpControlBarrierWaitEXT",
"class" : "Barrier",
"aliases" : [ "OpControlBarrierWaitINTEL" ],
"opcode" : 6143,
"operands" : [
{ "kind" : "IdScope", "name" : "Execution" },
{ "kind" : "IdScope", "name" : "Memory" },
{ "kind" : "IdMemorySemantics", "name" : "Semantics" }
],
"capabilities" : [ "SplitBarrierINTEL" ],
"capabilities" : [ "SplitBarrierEXT" ],
"version" : "None"
},
{
@@ -11538,6 +11628,34 @@
"provisional" : true,
"version" : "None"
},
{
"opname" : "OpPredicatedLoadINTEL",
"class" : "Memory",
"opcode" : 6258,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Pointer" },
{ "kind" : "IdRef", "name" : "Predicate" },
{ "kind" : "IdRef", "name" : "Default Value" },
{ "kind" : "MemoryAccess", "quantifier" : "?" }
],
"capabilities" : [ "PredicatedIOINTEL" ],
"version" : "None"
},
{
"opname" : "OpPredicatedStoreINTEL",
"class" : "Memory",
"opcode" : 6259,
"operands" : [
{ "kind" : "IdRef", "name" : "Pointer" },
{ "kind" : "IdRef", "name" : "Object" },
{ "kind" : "IdRef", "name" : "Predicate" },
{ "kind" : "MemoryAccess", "quantifier" : "?" }
],
"capabilities" : [ "PredicatedIOINTEL" ],
"version" : "None"
},
{
"opname" : "OpGroupIMulKHR",
"class" : "Group",
@@ -11728,6 +11846,48 @@
"capabilities" : [ "BindlessImagesINTEL" ],
"provisional" : true,
"version" : "None"
},
{
"opname" : "OpFDot2MixAcc32VALVE",
"class" : "Reserved",
"opcode" : 6916,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Vector 1" },
{ "kind" : "IdRef", "name" : "Vector 2" },
{ "kind" : "IdRef", "name" : "Accumulator" }
],
"capabilities" : [ "DotProductFloat16AccFloat32VALVE", "DotProductBFloat16AccVALVE" ],
"version" : "None"
},
{
"opname" : "OpFDot2MixAcc16VALVE",
"class" : "Reserved",
"opcode" : 6917,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Vector 1" },
{ "kind" : "IdRef", "name" : "Vector 2" },
{ "kind" : "IdRef", "name" : "Accumulator" }
],
"capabilities" : [ "DotProductFloat16AccFloat16VALVE", "DotProductBFloat16AccVALVE" ],
"version" : "None"
},
{
"opname" : "OpFDot4MixAcc32VALVE",
"class" : "Reserved",
"opcode" : 6918,
"operands" : [
{ "kind" : "IdResultType" },
{ "kind" : "IdResult" },
{ "kind" : "IdRef", "name" : "Vector 1" },
{ "kind" : "IdRef", "name" : "Vector 2" },
{ "kind" : "IdRef", "name" : "Accumulator" }
],
"capabilities" : [ "DotProductFloat8AccFloat32VALVE" ],
"version" : "None"
}
],
"operand_kinds" : [
@@ -12116,6 +12276,14 @@
],
"capabilities" : [ "FPGALoopControlsALTERA" ],
"version" : "None"
},
{
"enumerant" : "MultipleWaitQueuesQCOM",
"value" : "0x10000000",
"parameters" : [
{ "kind" : "LiteralInteger" }
],
"version" : "1.0"
}
]
},
@@ -12420,9 +12588,10 @@
"version" : "None"
},
{
"enumerant" : "ForceOpacityMicromap2StateEXT",
"enumerant" : "ForceOpacityMicromap2StateKHR",
"aliases" : [ "ForceOpacityMicromap2StateEXT" ],
"value" : "0x0400",
"capabilities" : [ "RayTracingOpacityMicromapEXT" ],
"capabilities" : [ "RayTracingOpacityMicromapKHR" ],
"version" : "None"
}
]
@@ -12552,6 +12721,16 @@
"enumerant" : "Rust",
"value" : 13,
"version" : "1.0"
},
{
"enumerant" : "Pred",
"value" : 14,
"version" : "1.0"
},
{
"enumerant" : "ApilaJai",
"value" : 15,
"version" : "1.0"
}
]
},
@@ -13239,6 +13418,13 @@
"provisional" : true,
"version" : "None"
},
{
"enumerant" : "ArithmeticPoisonKHR",
"value" : 5157,
"capabilities" : [ "PoisonFreezeKHR" ],
"provisional" : true,
"version" : "None"
},
{
"enumerant" : "OutputLinesEXT",
"aliases" : ["OutputLinesNV"],
@@ -13440,6 +13626,15 @@
"capabilities" : [ "FloatControls2" ],
"version" : "None"
},
{
"enumerant" : "OpacityMicromapIdKHR",
"value" : 6031,
"capabilities" : [ "RayTracingOpacityMicromapExecutionModeKHR" ],
"parameters" : [
{ "kind" : "IdRef", "name" : "Enable" }
],
"version" : "None"
},
{
"enumerant" : "StreamingInterfaceINTEL",
"value" : 6154,
@@ -14459,6 +14654,12 @@
"capabilities" : [ "Linkage" ],
"extensions" : [ "SPV_KHR_linkonce_odr" ],
"version" : "None"
},
{
"enumerant" : "WeakAMD",
"value" : 3,
"capabilities" : [ "WeakLinkageAMD" ],
"version" : "None"
}
]
},
@@ -15057,6 +15258,12 @@
],
"version" : "None"
},
{
"enumerant" : "UTFEncodedKHR",
"value" : 5145,
"capabilities" : [ "ConstantDataKHR" ],
"version" : "None"
},
{
"enumerant" : "OverrideCoverageNV",
"value" : 5248,
@@ -17233,6 +17440,36 @@
"extensions" : [ "SPV_EXT_float8"],
"version" : "None"
},
{
"enumerant" : "Float6EXT",
"value" : 4228,
"extensions" : [ "SPV_EXT_ocp_microscaling_types"],
"version" : "None"
},
{
"enumerant" : "Float4EXT",
"value" : 4229,
"extensions" : [ "SPV_EXT_ocp_microscaling_types"],
"version" : "None"
},
{
"enumerant" : "Float8UnsignedE8M0EXT",
"value" : 4230,
"extensions" : [ "SPV_EXT_ocp_microscaling_types"],
"version" : "None"
},
{
"enumerant" : "MXInt8EXT",
"value" : 4231,
"extensions" : [ "SPV_EXT_ocp_microscaling_types"],
"version" : "None"
},
{
"enumerant" : "BitcastExtractEXT",
"value" : 4232,
"extensions" : [ "SPV_EXT_ocp_microscaling_types"],
"version" : "None"
},
{
"enumerant" : "FragmentShadingRateKHR",
"value" : 4422,
@@ -17468,6 +17705,24 @@
"extensions" : [ "SPV_QCOM_image_processing2" ],
"version" : "None"
},
{
"enumerant" : "MultipleWaitQueuesQCOM",
"value" : 4539,
"extensions" : [ "SPV_QCOM_multiple_wait_queues" ],
"version" : "None"
},
{
"enumerant" : "ImageGatherLinearQCOM",
"value" : 4543,
"extensions" : [ "SPV_QCOM_image_processing3" ],
"version" : "None"
},
{
"enumerant" : "ImageGatherExtendedModesQCOM",
"value" : 4544,
"extensions" : [ "SPV_QCOM_image_processing3" ],
"version" : "None"
},
{
"enumerant" : "Float16ImageAMD",
"value" : 5008,
@@ -17563,6 +17818,12 @@
"extensions" : [ "SPV_KHR_bfloat16" ],
"version" : "None"
},
{
"enumerant" : "AbortKHR",
"value" : 5120,
"extensions" : [ "SPV_KHR_abort" ],
"version" : "None"
},
{
"enumerant" : "DescriptorHeapEXT",
"value": 5128,
@@ -17570,6 +17831,26 @@
"extensions" : [ "SPV_EXT_descriptor_heap" ],
"version" : "None"
},
{
"enumerant" : "ConstantDataKHR",
"value" : 5146,
"extensions" : [ "SPV_KHR_constant_data" ],
"version" : "None"
},
{
"enumerant" : "PoisonFreezeKHR",
"value" : 5156,
"extensions" : [ "SPV_KHR_poison_freeze" ],
"provisional" : true,
"version" : "None"
},
{
"enumerant" : "WeakLinkageAMD",
"value" : 5181,
"capabilities" : [ "Linkage" ],
"extensions" : [ "SPV_AMD_weak_linkage" ],
"version" : "None"
},
{
"enumerant" : "SampleMaskOverrideCoverageNV",
"value" : 5249,
@@ -17875,10 +18156,11 @@
"version" : "None"
},
{
"enumerant" : "RayTracingOpacityMicromapEXT",
"enumerant" : "RayTracingOpacityMicromapKHR",
"aliases" : ["RayTracingOpacityMicromapEXT"],
"value" : 5381,
"capabilities" : [ "Shader" ],
"extensions" : [ "SPV_EXT_opacity_micromap" ],
"extensions" : ["SPV_KHR_opacity_micromap", "SPV_EXT_opacity_micromap"],
"version" : "None"
},
{
@@ -18013,6 +18295,13 @@
"extensions" : [ "SPV_NV_tensor_addressing" ],
"version" : "None"
},
{
"enumerant" : "CooperativeMatrixDecodeVectorNV",
"value" : 5447,
"capabilities" : [ "CooperativeMatrixBlockLoadsNV" ],
"extensions" : [ "SPV_NV_cooperative_matrix_decode_vector" ],
"version" : "None"
},
{
"enumerant" : "SubgroupShuffleINTEL",
"value" : 5568,
@@ -18355,6 +18644,13 @@
"extensions" : [ "SPV_KHR_fma" ],
"version" : "None"
},
{
"enumerant" : "RayTracingOpacityMicromapExecutionModeKHR",
"value" : 6032,
"capabilities" : [ "Shader" ],
"extensions" : [ "SPV_KHR_opacity_micromap" ],
"version" : "None"
},
{
"enumerant" : "AtomicFloat32AddEXT",
"value" : 6033,
@@ -18399,9 +18695,10 @@
"version" : "None"
},
{
"enumerant" : "SplitBarrierINTEL",
"enumerant" : "SplitBarrierEXT",
"aliases" : [ "SplitBarrierINTEL" ],
"value" : 6141,
"extensions" : [ "SPV_INTEL_split_barrier" ],
"extensions" : [ "SPV_EXT_split_barrier", "SPV_INTEL_split_barrier" ],
"version" : "None"
},
{
@@ -18525,6 +18822,18 @@
"provisional" : true,
"version": "None"
},
{
"enumerant" : "PredicatedIOINTEL",
"value" : 6257,
"extensions" : [ "SPV_INTEL_predicated_io" ],
"version" : "None"
},
{
"enumerant" : "RoundedDivideSqrtINTEL",
"value" : 6265,
"extensions" : [ "SPV_INTEL_rounded_divide_sqrt" ],
"version": "None"
},
{
"enumerant" : "GroupUniformArithmeticKHR",
"value" : 6400,
@@ -18561,6 +18870,34 @@
"extensions" : [ "SPV_INTEL_bindless_images" ],
"provisional" : true,
"version" : "None"
},
{
"enumerant" : "DotProductFloat16AccFloat32VALVE",
"value" : 6912,
"capabilities" : [ "Float16" ],
"extensions" : [ "SPV_VALVE_mixed_float_dot_product" ],
"version" : "None"
},
{
"enumerant" : "DotProductFloat16AccFloat16VALVE",
"value" : 6913,
"capabilities" : [ "Float16" ],
"extensions" : [ "SPV_VALVE_mixed_float_dot_product" ],
"version" : "None"
},
{
"enumerant" : "DotProductBFloat16AccVALVE",
"value" : 6914,
"capabilities" : [ "BFloat16TypeKHR" ],
"extensions" : [ "SPV_VALVE_mixed_float_dot_product" ],
"version" : "None"
},
{
"enumerant" : "DotProductFloat8AccFloat32VALVE",
"value" : 6915,
"capabilities" : [ "Float8EXT" ],
"extensions" : [ "SPV_VALVE_mixed_float_dot_product" ],
"version" : "None"
}
]
},
@@ -18800,6 +19137,15 @@
],
"capabilities" : [ "CooperativeMatrixBlockLoadsNV" ],
"version" : "None"
},
{
"enumerant" : "DecodeVectorFunc",
"value" : "0x0004",
"parameters" : [
{ "kind" : "IdRef" }
],
"capabilities" : [ "CooperativeMatrixDecodeVectorNV" ],
"version" : "None"
}
]
},
@@ -19003,6 +19349,36 @@
"value" : 4215,
"capabilities" : [ "Float8EXT" ],
"version" : "None"
},
{
"enumerant" : "Float6E2M3EXT",
"value" : 4223,
"capabilities" : [ "Float6EXT" ],
"version" : "None"
},
{
"enumerant" : "Float6E3M2EXT",
"value" : 4224,
"capabilities" : [ "Float6EXT" ],
"version" : "None"
},
{
"enumerant" : "Float4E2M1EXT",
"value" : 4225,
"capabilities" : [ "Float4EXT" ],
"version" : "None"
},
{
"enumerant" : "Float8UnsignedE8M0EXT",
"value" : 4226,
"capabilities" : [ "Float8UnsignedE8M0EXT" ],
"version" : "None"
},
{
"enumerant" : "MXInt8EXT",
"value" : 4227,
"capabilities" : [ "MXInt8EXT" ],
"version" : "None"
}
]
},
@@ -19113,6 +19489,32 @@
}
]
},
{
"category" : "ValueEnum",
"kind" : "GatherModes",
"enumerants" : [
{
"enumerant" : "Gather4x1QCOM",
"value" : 0,
"version" : "None"
},
{
"enumerant" : "GatherDQCOM",
"value" : 1,
"version" : "None"
},
{
"enumerant" : "GatherH2QCOM",
"value" : 2,
"version" : "None"
},
{
"enumerant" : "GatherV2QCOM",
"value" : 3,
"version" : "None"
}
]
},
{
"category" : "Id",
"kind" : "IdResultType",
renderdoc/driver/shaders/spirv/spirv_debug.cpp
+14 -2
View File
@@ -5421,6 +5421,14 @@ void ThreadState::StepNext(bool useDebugState, const uint32_t steps,
case Op::HitObjectIsEmptyEXT:
case Op::HitObjectIsHitEXT:
case Op::HitObjectIsMissEXT:
case Op::AbortKHR:
case Op::PoisonKHR:
case Op::FreezeKHR:
case Op::BitcastExtractEXT:
case Op::FDot2MixAcc16VALVE:
case Op::FDot2MixAcc32VALVE:
case Op::FDot4MixAcc32VALVE:
case Op::ImageGatherQCOM:
{
RDCERR("Unsupported extension opcode used %s", ToStr(opdata.op).c_str());
@@ -5499,6 +5507,8 @@ void ThreadState::StepNext(bool useDebugState, const uint32_t steps,
case Op::TypeBufferEXT:
case Op::MemberDecorateIdEXT:
case Op::TypeHitObjectEXT:
case Op::ConstantDataKHR:
case Op::SpecConstantDataKHR:
{
RDCERR("Encountered unexpected global SPIR-V operation %s", ToStr(opdata.op).c_str());
break;
@@ -5564,8 +5574,8 @@ void ThreadState::StepNext(bool useDebugState, const uint32_t steps,
case Op::TypePipeStorage:
case Op::ConstantPipeStorage:
case Op::CreatePipeFromPipeStorage:
case Op::ControlBarrierArriveINTEL:
case Op::ControlBarrierWaitINTEL:
case Op::ControlBarrierArriveEXT:
case Op::ControlBarrierWaitEXT:
case Op::SubgroupMatrixMultiplyAccumulateINTEL:
case Op::SubgroupBlockPrefetchINTEL:
case Op::Subgroup2DBlockLoadINTEL:
@@ -5593,6 +5603,8 @@ void ThreadState::StepNext(bool useDebugState, const uint32_t steps,
case Op::ConvertHandleToSamplerINTEL:
case Op::SpecConstantCapabilitiesINTEL:
case Op::ConditionalCopyObjectINTEL:
case Op::PredicatedLoadINTEL:
case Op::PredicatedStoreINTEL:
{
// these are kernel only
RDCERR("Encountered unexpected kernel SPIR-V operation %s", ToStr(opdata.op).c_str());
renderdoc/driver/shaders/spirv/spirv_debug_setup.cpp
+34 -2
View File
@@ -721,7 +721,8 @@ void Reflector::CheckDebuggable(bool &debuggable, rdcstr &debugStatus) const
case Capability::RayTracingKHR:
case Capability::RayTracingPositionFetchKHR:
case Capability::RayTraversalPrimitiveCullingKHR:
case Capability::RayTracingOpacityMicromapEXT:
case Capability::RayTracingOpacityMicromapKHR:
case Capability::RayTracingOpacityMicromapExecutionModeKHR:
{
supported = false;
break;
@@ -793,6 +794,21 @@ void Reflector::CheckDebuggable(bool &debuggable, rdcstr &debugStatus) const
break;
}
// SPV_KHR_constant_data & SPV_KHR_abort
case Capability::AbortKHR:
case Capability::ConstantDataKHR:
{
supported = false;
break;
}
// SPV_KHR_poison_freeze
case Capability::PoisonFreezeKHR:
{
supported = false;
break;
}
// no plans to support these - mostly Kernel/OpenCL related or vendor extensions
case Capability::Addresses:
case Capability::Linkage:
@@ -861,7 +877,7 @@ void Reflector::CheckDebuggable(bool &debuggable, rdcstr &debugStatus) const
case Capability::DebugInfoModuleINTEL:
case Capability::BindlessTextureNV:
case Capability::MemoryAccessAliasingINTEL:
case Capability::SplitBarrierINTEL:
case Capability::SplitBarrierEXT:
case Capability::GroupUniformArithmeticKHR:
case Capability::CoreBuiltinsARM:
case Capability::FPGADSPControlALTERA:
@@ -927,6 +943,22 @@ void Reflector::CheckDebuggable(bool &debuggable, rdcstr &debugStatus) const
case Capability::RayTracingNV:
case Capability::ShaderInvocationReorderNV:
case Capability::PushConstantBanksNV:
case Capability::MultipleWaitQueuesQCOM:
case Capability::Float6EXT:
case Capability::Float4EXT:
case Capability::Float8UnsignedE8M0EXT:
case Capability::MXInt8EXT:
case Capability::DotProductBFloat16AccVALVE:
case Capability::DotProductFloat16AccFloat16VALVE:
case Capability::DotProductFloat16AccFloat32VALVE:
case Capability::DotProductFloat8AccFloat32VALVE:
case Capability::WeakLinkageAMD:
case Capability::PredicatedIOINTEL:
case Capability::RoundedDivideSqrtINTEL:
case Capability::ImageGatherLinearQCOM:
case Capability::ImageGatherExtendedModesQCOM:
case Capability::CooperativeMatrixDecodeVectorNV:
case Capability::BitcastExtractEXT:
case Capability::Max:
case Capability::Invalid:
{
renderdoc/driver/shaders/spirv/spirv_gen.cpp
+303 -20
View File
@@ -131,6 +131,7 @@ rdcstr DoStringise(const rdcspv::LoopControl &el)
STRINGISE_BITFIELD_CLASS_BIT(NoFusionALTERA);
STRINGISE_BITFIELD_CLASS_BIT(LoopCountALTERA);
STRINGISE_BITFIELD_CLASS_BIT(MaxReinvocationDelayALTERA);
STRINGISE_BITFIELD_CLASS_BIT(MultipleWaitQueuesQCOM);
}
END_BITFIELD_STRINGISE();
}
@@ -223,7 +224,7 @@ rdcstr DoStringise(const rdcspv::RayFlags &el)
STRINGISE_BITFIELD_CLASS_BIT(CullNoOpaqueKHR);
STRINGISE_BITFIELD_CLASS_BIT(SkipTrianglesKHR);
STRINGISE_BITFIELD_CLASS_BIT(SkipAABBsKHR);
STRINGISE_BITFIELD_CLASS_BIT(ForceOpacityMicromap2StateEXT);
STRINGISE_BITFIELD_CLASS_BIT(ForceOpacityMicromap2StateKHR);
}
END_BITFIELD_STRINGISE();
}
@@ -273,6 +274,8 @@ rdcstr DoStringise(const rdcspv::SourceLanguage &el)
STRINGISE_ENUM_CLASS(Slang);
STRINGISE_ENUM_CLASS(Zig);
STRINGISE_ENUM_CLASS(Rust);
STRINGISE_ENUM_CLASS(Pred);
STRINGISE_ENUM_CLASS(ApilaJai);
}
END_ENUM_STRINGISE();
}
@@ -399,6 +402,7 @@ rdcstr DoStringise(const rdcspv::ExecutionMode &el)
STRINGISE_ENUM_CLASS(QuadDerivativesKHR);
STRINGISE_ENUM_CLASS(RequireFullQuadsKHR);
STRINGISE_ENUM_CLASS(SharesInputWithAMDX);
STRINGISE_ENUM_CLASS(ArithmeticPoisonKHR);
STRINGISE_ENUM_CLASS(OutputLinesEXT);
STRINGISE_ENUM_CLASS(OutputPrimitivesEXT);
STRINGISE_ENUM_CLASS(DerivativeGroupQuadsKHR);
@@ -423,6 +427,7 @@ rdcstr DoStringise(const rdcspv::ExecutionMode &el)
STRINGISE_ENUM_CLASS(SchedulerTargetFmaxMhzINTEL);
STRINGISE_ENUM_CLASS(MaximallyReconvergesKHR);
STRINGISE_ENUM_CLASS(FPFastMathDefault);
STRINGISE_ENUM_CLASS(OpacityMicromapIdKHR);
STRINGISE_ENUM_CLASS(StreamingInterfaceINTEL);
STRINGISE_ENUM_CLASS(RegisterMapInterfaceINTEL);
STRINGISE_ENUM_CLASS(NamedBarrierCountINTEL);
@@ -700,6 +705,7 @@ rdcstr DoStringise(const rdcspv::LinkageType &el)
STRINGISE_ENUM_CLASS(Export);
STRINGISE_ENUM_CLASS(Import);
STRINGISE_ENUM_CLASS(LinkOnceODR);
STRINGISE_ENUM_CLASS(WeakAMD);
}
END_ENUM_STRINGISE();
}
@@ -816,6 +822,7 @@ rdcstr DoStringise(const rdcspv::Decoration &el)
STRINGISE_ENUM_CLASS(PayloadDispatchIndirectAMDX);
STRINGISE_ENUM_CLASS(ArrayStrideIdEXT);
STRINGISE_ENUM_CLASS(OffsetIdEXT);
STRINGISE_ENUM_CLASS(UTFEncodedKHR);
STRINGISE_ENUM_CLASS(OverrideCoverageNV);
STRINGISE_ENUM_CLASS(PassthroughNV);
STRINGISE_ENUM_CLASS(ViewportRelativeNV);
@@ -1170,6 +1177,11 @@ rdcstr DoStringise(const rdcspv::Capability &el)
STRINGISE_ENUM_CLASS(CooperativeMatrixLayoutsARM);
STRINGISE_ENUM_CLASS(Float8EXT);
STRINGISE_ENUM_CLASS(Float8CooperativeMatrixEXT);
STRINGISE_ENUM_CLASS(Float6EXT);
STRINGISE_ENUM_CLASS(Float4EXT);
STRINGISE_ENUM_CLASS(Float8UnsignedE8M0EXT);
STRINGISE_ENUM_CLASS(MXInt8EXT);
STRINGISE_ENUM_CLASS(BitcastExtractEXT);
STRINGISE_ENUM_CLASS(FragmentShadingRateKHR);
STRINGISE_ENUM_CLASS(SubgroupBallotKHR);
STRINGISE_ENUM_CLASS(DrawParameters);
@@ -1206,6 +1218,9 @@ rdcstr DoStringise(const rdcspv::Capability &el)
STRINGISE_ENUM_CLASS(TileShadingQCOM);
STRINGISE_ENUM_CLASS(CooperativeMatrixConversionQCOM);
STRINGISE_ENUM_CLASS(TextureBlockMatch2QCOM);
STRINGISE_ENUM_CLASS(MultipleWaitQueuesQCOM);
STRINGISE_ENUM_CLASS(ImageGatherLinearQCOM);
STRINGISE_ENUM_CLASS(ImageGatherExtendedModesQCOM);
STRINGISE_ENUM_CLASS(Float16ImageAMD);
STRINGISE_ENUM_CLASS(ImageGatherBiasLodAMD);
STRINGISE_ENUM_CLASS(FragmentMaskAMD);
@@ -1220,7 +1235,11 @@ rdcstr DoStringise(const rdcspv::Capability &el)
STRINGISE_ENUM_CLASS(BFloat16TypeKHR);
STRINGISE_ENUM_CLASS(BFloat16DotProductKHR);
STRINGISE_ENUM_CLASS(BFloat16CooperativeMatrixKHR);
STRINGISE_ENUM_CLASS(AbortKHR);
STRINGISE_ENUM_CLASS(DescriptorHeapEXT);
STRINGISE_ENUM_CLASS(ConstantDataKHR);
STRINGISE_ENUM_CLASS(PoisonFreezeKHR);
STRINGISE_ENUM_CLASS(WeakLinkageAMD);
STRINGISE_ENUM_CLASS(SampleMaskOverrideCoverageNV);
STRINGISE_ENUM_CLASS(GeometryShaderPassthroughNV);
STRINGISE_ENUM_CLASS(ShaderViewportIndexLayerEXT);
@@ -1259,7 +1278,7 @@ rdcstr DoStringise(const rdcspv::Capability &el)
STRINGISE_ENUM_CLASS(FragmentShaderPixelInterlockEXT);
STRINGISE_ENUM_CLASS(DemoteToHelperInvocation);
STRINGISE_ENUM_CLASS(DisplacementMicromapNV);
STRINGISE_ENUM_CLASS(RayTracingOpacityMicromapEXT);
STRINGISE_ENUM_CLASS(RayTracingOpacityMicromapKHR);
STRINGISE_ENUM_CLASS(ShaderInvocationReorderEXT);
STRINGISE_ENUM_CLASS(BindlessTextureNV);
STRINGISE_ENUM_CLASS(RayQueryPositionFetchKHR);
@@ -1280,6 +1299,7 @@ rdcstr DoStringise(const rdcspv::Capability &el)
STRINGISE_ENUM_CLASS(CooperativeVectorTrainingNV);
STRINGISE_ENUM_CLASS(RayTracingClusterAccelerationStructureNV);
STRINGISE_ENUM_CLASS(TensorAddressingNV);
STRINGISE_ENUM_CLASS(CooperativeMatrixDecodeVectorNV);
STRINGISE_ENUM_CLASS(SubgroupShuffleINTEL);
STRINGISE_ENUM_CLASS(SubgroupBufferBlockIOINTEL);
STRINGISE_ENUM_CLASS(SubgroupImageBlockIOINTEL);
@@ -1333,6 +1353,7 @@ rdcstr DoStringise(const rdcspv::Capability &el)
STRINGISE_ENUM_CLASS(GroupNonUniformRotateKHR);
STRINGISE_ENUM_CLASS(FloatControls2);
STRINGISE_ENUM_CLASS(FMAKHR);
STRINGISE_ENUM_CLASS(RayTracingOpacityMicromapExecutionModeKHR);
STRINGISE_ENUM_CLASS(AtomicFloat32AddEXT);
STRINGISE_ENUM_CLASS(AtomicFloat64AddEXT);
STRINGISE_ENUM_CLASS(LongCompositesINTEL);
@@ -1340,7 +1361,7 @@ rdcstr DoStringise(const rdcspv::Capability &el)
STRINGISE_ENUM_CLASS(AtomicFloat16AddEXT);
STRINGISE_ENUM_CLASS(DebugInfoModuleINTEL);
STRINGISE_ENUM_CLASS(BFloat16ConversionINTEL);
STRINGISE_ENUM_CLASS(SplitBarrierINTEL);
STRINGISE_ENUM_CLASS(SplitBarrierEXT);
STRINGISE_ENUM_CLASS(ArithmeticFenceEXT);
STRINGISE_ENUM_CLASS(FPGAClusterAttributesV2ALTERA);
STRINGISE_ENUM_CLASS(FPGAKernelAttributesv2INTEL);
@@ -1359,12 +1380,18 @@ rdcstr DoStringise(const rdcspv::Capability &el)
STRINGISE_ENUM_CLASS(UntypedVariableLengthArrayINTEL);
STRINGISE_ENUM_CLASS(SpecConditionalINTEL);
STRINGISE_ENUM_CLASS(FunctionVariantsINTEL);
STRINGISE_ENUM_CLASS(PredicatedIOINTEL);
STRINGISE_ENUM_CLASS(RoundedDivideSqrtINTEL);
STRINGISE_ENUM_CLASS(GroupUniformArithmeticKHR);
STRINGISE_ENUM_CLASS(TensorFloat32RoundingINTEL);
STRINGISE_ENUM_CLASS(MaskedGatherScatterINTEL);
STRINGISE_ENUM_CLASS(CacheControlsINTEL);
STRINGISE_ENUM_CLASS(RegisterLimitsINTEL);
STRINGISE_ENUM_CLASS(BindlessImagesINTEL);
STRINGISE_ENUM_CLASS(DotProductFloat16AccFloat32VALVE);
STRINGISE_ENUM_CLASS(DotProductFloat16AccFloat16VALVE);
STRINGISE_ENUM_CLASS(DotProductBFloat16AccVALVE);
STRINGISE_ENUM_CLASS(DotProductFloat8AccFloat32VALVE);
}
END_ENUM_STRINGISE();
}
@@ -1489,6 +1516,7 @@ rdcstr DoStringise(const rdcspv::TensorAddressingOperands &el)
STRINGISE_BITFIELD_CLASS_BIT(TensorView);
STRINGISE_BITFIELD_CLASS_BIT(DecodeFunc);
STRINGISE_BITFIELD_CLASS_BIT(DecodeVectorFunc);
}
END_BITFIELD_STRINGISE();
}
@@ -1574,6 +1602,11 @@ rdcstr DoStringise(const rdcspv::FPEncoding &el)
STRINGISE_ENUM_CLASS(BFloat16KHR);
STRINGISE_ENUM_CLASS(Float8E4M3EXT);
STRINGISE_ENUM_CLASS(Float8E5M2EXT);
STRINGISE_ENUM_CLASS(Float6E2M3EXT);
STRINGISE_ENUM_CLASS(Float6E3M2EXT);
STRINGISE_ENUM_CLASS(Float4E2M1EXT);
STRINGISE_ENUM_CLASS(Float8UnsignedE8M0EXT);
STRINGISE_ENUM_CLASS(MXInt8EXT);
}
END_ENUM_STRINGISE();
}
@@ -1615,6 +1648,19 @@ rdcstr DoStringise(const rdcspv::ComponentType &el)
END_ENUM_STRINGISE();
}
template <>
rdcstr DoStringise(const rdcspv::GatherModes &el)
{
BEGIN_ENUM_STRINGISE(rdcspv::GatherModes);
{
STRINGISE_ENUM_CLASS(Gather4x1QCOM);
STRINGISE_ENUM_CLASS(GatherDQCOM);
STRINGISE_ENUM_CLASS(GatherH2QCOM);
STRINGISE_ENUM_CLASS(GatherV2QCOM);
}
END_ENUM_STRINGISE();
}
template <>
rdcstr DoStringise(const rdcspv::TensorOperands &el)
{
@@ -1994,6 +2040,7 @@ rdcstr DoStringise(const rdcspv::Op &el)
STRINGISE_ENUM_CLASS(GraphSetOutputARM);
STRINGISE_ENUM_CLASS(GraphEndARM);
STRINGISE_ENUM_CLASS(TypeGraphARM);
STRINGISE_ENUM_CLASS(BitcastExtractEXT);
STRINGISE_ENUM_CLASS(TerminateInvocation);
STRINGISE_ENUM_CLASS(TypeUntypedPointerKHR);
STRINGISE_ENUM_CLASS(UntypedVariableKHR);
@@ -2051,6 +2098,7 @@ rdcstr DoStringise(const rdcspv::Op &el)
STRINGISE_ENUM_CLASS(CompositeConstructCoopMatQCOM);
STRINGISE_ENUM_CLASS(CompositeExtractCoopMatQCOM);
STRINGISE_ENUM_CLASS(ExtractSubArrayQCOM);
STRINGISE_ENUM_CLASS(ImageGatherQCOM);
STRINGISE_ENUM_CLASS(GroupIAddNonUniformAMD);
STRINGISE_ENUM_CLASS(GroupFAddNonUniformAMD);
STRINGISE_ENUM_CLASS(GroupFMinNonUniformAMD);
@@ -2074,9 +2122,14 @@ rdcstr DoStringise(const rdcspv::Op &el)
STRINGISE_ENUM_CLASS(GroupNonUniformQuadAnyKHR);
STRINGISE_ENUM_CLASS(TypeBufferEXT);
STRINGISE_ENUM_CLASS(BufferPointerEXT);
STRINGISE_ENUM_CLASS(AbortKHR);
STRINGISE_ENUM_CLASS(UntypedImageTexelPointerEXT);
STRINGISE_ENUM_CLASS(MemberDecorateIdEXT);
STRINGISE_ENUM_CLASS(ConstantSizeOfEXT);
STRINGISE_ENUM_CLASS(ConstantDataKHR);
STRINGISE_ENUM_CLASS(SpecConstantDataKHR);
STRINGISE_ENUM_CLASS(PoisonKHR);
STRINGISE_ENUM_CLASS(FreezeKHR);
STRINGISE_ENUM_CLASS(HitObjectRecordHitMotionNV);
STRINGISE_ENUM_CLASS(HitObjectRecordHitWithIndexMotionNV);
STRINGISE_ENUM_CLASS(HitObjectRecordMissMotionNV);
@@ -2278,8 +2331,8 @@ rdcstr DoStringise(const rdcspv::Op &el)
STRINGISE_ENUM_CLASS(CompositeConstructContinuedINTEL);
STRINGISE_ENUM_CLASS(ConvertFToBF16INTEL);
STRINGISE_ENUM_CLASS(ConvertBF16ToFINTEL);
STRINGISE_ENUM_CLASS(ControlBarrierArriveINTEL);
STRINGISE_ENUM_CLASS(ControlBarrierWaitINTEL);
STRINGISE_ENUM_CLASS(ControlBarrierArriveEXT);
STRINGISE_ENUM_CLASS(ControlBarrierWaitEXT);
STRINGISE_ENUM_CLASS(ArithmeticFenceEXT);
STRINGISE_ENUM_CLASS(SubgroupBlockPrefetchINTEL);
STRINGISE_ENUM_CLASS(Subgroup2DBlockLoadINTEL);
@@ -2297,6 +2350,8 @@ rdcstr DoStringise(const rdcspv::Op &el)
STRINGISE_ENUM_CLASS(SpecConstantArchitectureINTEL);
STRINGISE_ENUM_CLASS(SpecConstantCapabilitiesINTEL);
STRINGISE_ENUM_CLASS(ConditionalCopyObjectINTEL);
STRINGISE_ENUM_CLASS(PredicatedLoadINTEL);
STRINGISE_ENUM_CLASS(PredicatedStoreINTEL);
STRINGISE_ENUM_CLASS(GroupIMulKHR);
STRINGISE_ENUM_CLASS(GroupFMulKHR);
STRINGISE_ENUM_CLASS(GroupBitwiseAndKHR);
@@ -2311,6 +2366,9 @@ rdcstr DoStringise(const rdcspv::Op &el)
STRINGISE_ENUM_CLASS(ConvertHandleToImageINTEL);
STRINGISE_ENUM_CLASS(ConvertHandleToSamplerINTEL);
STRINGISE_ENUM_CLASS(ConvertHandleToSampledImageINTEL);
STRINGISE_ENUM_CLASS(FDot2MixAcc32VALVE);
STRINGISE_ENUM_CLASS(FDot2MixAcc16VALVE);
STRINGISE_ENUM_CLASS(FDot4MixAcc32VALVE);
}
END_ENUM_STRINGISE();
}
@@ -2434,6 +2492,8 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
ret += "LoopCountALTERA" "(" + ToStr(el.loopCountALTERA) + ")" ", ";
if(el.flags & LoopControl::MaxReinvocationDelayALTERA)
ret += "MaxReinvocationDelayALTERA" "(" + ToStr(el.maxReinvocationDelayALTERA) + ")" ", ";
if(el.flags & LoopControl::MultipleWaitQueuesQCOM)
ret += "MultipleWaitQueuesQCOM" "(" + ToStr(el.multipleWaitQueuesQCOM) + ")" ", ";
// remove trailing ", "
if(ret.size() > 2)
@@ -2546,6 +2606,8 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
ret += "(" + ToStr(el.schedulerTargetFmaxMhzINTEL) + ")"; break;
case ExecutionMode::FPFastMathDefault:
ret += "(" + idName(el.fPFastMathDefault.targetType) + ", " + idName(el.fPFastMathDefault.fastMathMode) + ")"; break;
case ExecutionMode::OpacityMicromapIdKHR:
ret += "(" + idName(el.opacityMicromapIdKHR) + ")"; break;
case ExecutionMode::StreamingInterfaceINTEL:
ret += "(" + ToStr(el.streamingInterfaceINTEL) + ")"; break;
case ExecutionMode::RegisterMapInterfaceINTEL:
@@ -2732,6 +2794,8 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
ret += "TensorView" "(" + idName(el.tensorView) + ")" ", ";
if(el.flags & TensorAddressingOperands::DecodeFunc)
ret += "DecodeFunc" "(" + idName(el.decodeFunc) + ")" ", ";
if(el.flags & TensorAddressingOperands::DecodeVectorFunc)
ret += "DecodeVectorFunc" "(" + idName(el.decodeVectorFunc) + ")" ", ";
// remove trailing ", "
if(ret.size() > 2)
@@ -4733,6 +4797,12 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
callback(Id::fromWord(it.word(1)), true);
for(size_t i=0; i < size-3; i++) callback(Id::fromWord(it.word(3+i)), false);
break;
case rdcspv::Op::BitcastExtractEXT:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
callback(Id::fromWord(it.word(4)), false);
break;
case rdcspv::Op::TerminateInvocation:
break;
case rdcspv::Op::TypeUntypedPointerKHR:
@@ -5082,6 +5152,14 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
callback(Id::fromWord(it.word(3)), false);
callback(Id::fromWord(it.word(4)), false);
break;
case rdcspv::Op::ImageGatherQCOM:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
callback(Id::fromWord(it.word(4)), false);
callback(Id::fromWord(it.word(5)), false);
callback(Id::fromWord(it.word(6)), false);
break;
case rdcspv::Op::GroupIAddNonUniformAMD:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
@@ -5202,6 +5280,10 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
break;
case rdcspv::Op::AbortKHR:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), false);
break;
case rdcspv::Op::UntypedImageTexelPointerEXT:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
@@ -5218,6 +5300,23 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
break;
case rdcspv::Op::ConstantDataKHR:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
break;
case rdcspv::Op::SpecConstantDataKHR:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
break;
case rdcspv::Op::PoisonKHR:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
break;
case rdcspv::Op::FreezeKHR:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
break;
case rdcspv::Op::HitObjectRecordHitMotionNV:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), false);
@@ -5558,6 +5657,7 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
callback(Id::fromWord(it.word(2)), false);
callback(Id::fromWord(it.word(3)), false);
callback(Id::fromWord(it.word(4)), false);
if(5 < size) callback(Id::fromWord(it.word(5)), false);
break;
case rdcspv::Op::HitObjectRecordMissEXT:
callback(Id::fromWord(it.word(1)), false);
@@ -6413,9 +6513,7 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
for(size_t i=0; i < size-1; i++) callback(Id::fromWord(it.word(1+i)), false);
break;
case rdcspv::Op::CompositeConstructContinuedINTEL:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
for(size_t i=0; i < size-3; i++) callback(Id::fromWord(it.word(3+i)), false);
for(size_t i=0; i < size-1; i++) callback(Id::fromWord(it.word(1+i)), false);
break;
case rdcspv::Op::ConvertFToBF16INTEL:
callback(Id::fromWord(it.word(1)), false);
@@ -6427,12 +6525,12 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
break;
case rdcspv::Op::ControlBarrierArriveINTEL:
case rdcspv::Op::ControlBarrierArriveEXT:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), false);
callback(Id::fromWord(it.word(3)), false);
break;
case rdcspv::Op::ControlBarrierWaitINTEL:
case rdcspv::Op::ControlBarrierWaitEXT:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), false);
callback(Id::fromWord(it.word(3)), false);
@@ -6557,6 +6655,18 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
callback(Id::fromWord(it.word(2)), true);
for(size_t i=0; i < size-3; i++) callback(Id::fromWord(it.word(3+i)), false);
break;
case rdcspv::Op::PredicatedLoadINTEL:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
callback(Id::fromWord(it.word(4)), false);
callback(Id::fromWord(it.word(5)), false);
break;
case rdcspv::Op::PredicatedStoreINTEL:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), false);
callback(Id::fromWord(it.word(3)), false);
break;
case rdcspv::Op::GroupIMulKHR:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
@@ -6637,6 +6747,27 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
break;
case rdcspv::Op::FDot2MixAcc32VALVE:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
callback(Id::fromWord(it.word(4)), false);
callback(Id::fromWord(it.word(5)), false);
break;
case rdcspv::Op::FDot2MixAcc16VALVE:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
callback(Id::fromWord(it.word(4)), false);
callback(Id::fromWord(it.word(5)), false);
break;
case rdcspv::Op::FDot4MixAcc32VALVE:
callback(Id::fromWord(it.word(1)), false);
callback(Id::fromWord(it.word(2)), true);
callback(Id::fromWord(it.word(3)), false);
callback(Id::fromWord(it.word(4)), false);
callback(Id::fromWord(it.word(5)), false);
break;
case Op::Max: break;
}
}
@@ -10675,6 +10806,17 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ")";
break;
}
case rdcspv::Op::BitcastExtractEXT:
{
OpBitcastExtractEXT decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("BitcastExtractEXT("_lit)
+ ParamToStr(idName, decoded.base)
+ ", "
+ ParamToStr(idName, decoded.offset)
+ ")";
break;
}
case rdcspv::Op::TerminateInvocation:
{
OpTerminateInvocation decoded(it);
@@ -11372,6 +11514,22 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ")";
break;
}
case rdcspv::Op::ImageGatherQCOM:
{
OpImageGatherQCOM decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("ImageGatherQCOM("_lit)
+ ParamToStr(idName, decoded.sampledImage)
+ ", "
+ ParamToStr(idName, decoded.coordinate)
+ ", "
+ ParamToStr(idName, decoded.component)
+ ", "
+ ParamToStr(idName, decoded.mode)
+ (7 < size ? ", " + ParamToStr(idName, decoded.imageOperands) : "")
+ ")";
break;
}
case rdcspv::Op::GroupIAddNonUniformAMD:
{
OpGroupIAddNonUniformAMD decoded(it);
@@ -11622,6 +11780,16 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ")";
break;
}
case rdcspv::Op::AbortKHR:
{
OpAbortKHR decoded(it);
ret += rdcstr("AbortKHR("_lit)
+ ParamToStr(idName, decoded.messageType)
+ ", "
+ ParamToStr(idName, decoded.message)
+ ")";
break;
}
case rdcspv::Op::UntypedImageTexelPointerEXT:
{
OpUntypedImageTexelPointerEXT decoded(it);
@@ -11658,6 +11826,41 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ")";
break;
}
case rdcspv::Op::ConstantDataKHR:
{
OpConstantDataKHR decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("ConstantDataKHR("_lit)
+ ParamsToStr(idName, decoded.data)
+ ")";
break;
}
case rdcspv::Op::SpecConstantDataKHR:
{
OpSpecConstantDataKHR decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("SpecConstantDataKHR("_lit)
+ ParamsToStr(idName, decoded.data)
+ ")";
break;
}
case rdcspv::Op::PoisonKHR:
{
OpPoisonKHR decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("PoisonKHR("_lit)
+ ")";
break;
}
case rdcspv::Op::FreezeKHR:
{
OpFreezeKHR decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("FreezeKHR("_lit)
+ ParamToStr(idName, decoded.value)
+ ")";
break;
}
case rdcspv::Op::HitObjectRecordHitMotionNV:
{
OpHitObjectRecordHitMotionNV decoded(it);
@@ -12352,6 +12555,7 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ParamToStr(idName, decoded.sBTRecordIndex)
+ ", "
+ ParamToStr(idName, decoded.hitObjectAttributes)
+ (5 < size ? ", " + ParamToStr(idName, decoded.hitKind) : "")
+ ")";
break;
}
@@ -14063,7 +14267,6 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
case rdcspv::Op::CompositeConstructContinuedINTEL:
{
OpCompositeConstructContinuedINTEL decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("CompositeConstructContinuedINTEL("_lit)
+ ParamsToStr(idName, decoded.constituents)
+ ")";
@@ -14087,10 +14290,10 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ")";
break;
}
case rdcspv::Op::ControlBarrierArriveINTEL:
case rdcspv::Op::ControlBarrierArriveEXT:
{
OpControlBarrierArriveINTEL decoded(it);
ret += rdcstr("ControlBarrierArriveINTEL("_lit)
OpControlBarrierArriveEXT decoded(it);
ret += rdcstr("ControlBarrierArriveEXT("_lit)
+ ToStr(Scope(constIntVal(decoded.execution)))
+ ", "
+ ToStr(Scope(constIntVal(decoded.memory)))
@@ -14099,10 +14302,10 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ")";
break;
}
case rdcspv::Op::ControlBarrierWaitINTEL:
case rdcspv::Op::ControlBarrierWaitEXT:
{
OpControlBarrierWaitINTEL decoded(it);
ret += rdcstr("ControlBarrierWaitINTEL("_lit)
OpControlBarrierWaitEXT decoded(it);
ret += rdcstr("ControlBarrierWaitEXT("_lit)
+ ToStr(Scope(constIntVal(decoded.execution)))
+ ", "
+ ToStr(Scope(constIntVal(decoded.memory)))
@@ -14381,6 +14584,33 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ")";
break;
}
case rdcspv::Op::PredicatedLoadINTEL:
{
OpPredicatedLoadINTEL decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("PredicatedLoadINTEL("_lit)
+ ParamToStr(idName, decoded.pointer)
+ ", "
+ ParamToStr(idName, decoded.predicate)
+ ", "
+ ParamToStr(idName, decoded.defaultValue)
+ (6 < size ? ", " + ParamToStr(idName, decoded.memoryAccess) : "")
+ ")";
break;
}
case rdcspv::Op::PredicatedStoreINTEL:
{
OpPredicatedStoreINTEL decoded(it);
ret += rdcstr("PredicatedStoreINTEL("_lit)
+ ParamToStr(idName, decoded.pointer)
+ ", "
+ ParamToStr(idName, decoded.object)
+ ", "
+ ParamToStr(idName, decoded.predicate)
+ (4 < size ? ", " + ParamToStr(idName, decoded.memoryAccess) : "")
+ ")";
break;
}
case rdcspv::Op::GroupIMulKHR:
{
OpGroupIMulKHR decoded(it);
@@ -14550,6 +14780,45 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
+ ")";
break;
}
case rdcspv::Op::FDot2MixAcc32VALVE:
{
OpFDot2MixAcc32VALVE decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("FDot2MixAcc32VALVE("_lit)
+ ParamToStr(idName, decoded.vector1)
+ ", "
+ ParamToStr(idName, decoded.vector2)
+ ", "
+ ParamToStr(idName, decoded.accumulator)
+ ")";
break;
}
case rdcspv::Op::FDot2MixAcc16VALVE:
{
OpFDot2MixAcc16VALVE decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("FDot2MixAcc16VALVE("_lit)
+ ParamToStr(idName, decoded.vector1)
+ ", "
+ ParamToStr(idName, decoded.vector2)
+ ", "
+ ParamToStr(idName, decoded.accumulator)
+ ")";
break;
}
case rdcspv::Op::FDot4MixAcc32VALVE:
{
OpFDot4MixAcc32VALVE decoded(it);
ret += declName(decoded.resultType, decoded.result) + " = ";
ret += rdcstr("FDot4MixAcc32VALVE("_lit)
+ ParamToStr(idName, decoded.vector1)
+ ", "
+ ParamToStr(idName, decoded.vector2)
+ ", "
+ ParamToStr(idName, decoded.accumulator)
+ ")";
break;
}
case Op::Max: break;
}
return ret;
@@ -14919,6 +15188,7 @@ OpDecoder::OpDecoder(const ConstIter &it)
case rdcspv::Op::GraphSetOutputARM: result = Id(); resultType = Id(); break;
case rdcspv::Op::GraphEndARM: result = Id(); resultType = Id(); break;
case rdcspv::Op::TypeGraphARM: result = Id::fromWord(it.word(1)); resultType = Id(); break;
case rdcspv::Op::BitcastExtractEXT: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::TerminateInvocation: result = Id(); resultType = Id(); break;
case rdcspv::Op::TypeUntypedPointerKHR: result = Id::fromWord(it.word(1)); resultType = Id(); break;
case rdcspv::Op::UntypedVariableKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
@@ -14976,6 +15246,7 @@ OpDecoder::OpDecoder(const ConstIter &it)
case rdcspv::Op::CompositeConstructCoopMatQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::CompositeExtractCoopMatQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::ExtractSubArrayQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::ImageGatherQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::GroupIAddNonUniformAMD: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::GroupFAddNonUniformAMD: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::GroupFMinNonUniformAMD: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
@@ -14999,9 +15270,14 @@ OpDecoder::OpDecoder(const ConstIter &it)
case rdcspv::Op::GroupNonUniformQuadAnyKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::TypeBufferEXT: result = Id::fromWord(it.word(1)); resultType = Id(); break;
case rdcspv::Op::BufferPointerEXT: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::AbortKHR: result = Id(); resultType = Id(); break;
case rdcspv::Op::UntypedImageTexelPointerEXT: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::MemberDecorateIdEXT: result = Id(); resultType = Id(); break;
case rdcspv::Op::ConstantSizeOfEXT: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::ConstantDataKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::SpecConstantDataKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::PoisonKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::FreezeKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::HitObjectRecordHitMotionNV: result = Id(); resultType = Id(); break;
case rdcspv::Op::HitObjectRecordHitWithIndexMotionNV: result = Id(); resultType = Id(); break;
case rdcspv::Op::HitObjectRecordMissMotionNV: result = Id(); resultType = Id(); break;
@@ -15200,11 +15476,11 @@ OpDecoder::OpDecoder(const ConstIter &it)
case rdcspv::Op::TypeStructContinuedINTEL: result = Id(); resultType = Id(); break;
case rdcspv::Op::ConstantCompositeContinuedINTEL: result = Id(); resultType = Id(); break;
case rdcspv::Op::SpecConstantCompositeContinuedINTEL: result = Id(); resultType = Id(); break;
case rdcspv::Op::CompositeConstructContinuedINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::CompositeConstructContinuedINTEL: result = Id(); resultType = Id(); break;
case rdcspv::Op::ConvertFToBF16INTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::ConvertBF16ToFINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::ControlBarrierArriveINTEL: result = Id(); resultType = Id(); break;
case rdcspv::Op::ControlBarrierWaitINTEL: result = Id(); resultType = Id(); break;
case rdcspv::Op::ControlBarrierArriveEXT: result = Id(); resultType = Id(); break;
case rdcspv::Op::ControlBarrierWaitEXT: result = Id(); resultType = Id(); break;
case rdcspv::Op::ArithmeticFenceEXT: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::SubgroupBlockPrefetchINTEL: result = Id(); resultType = Id(); break;
case rdcspv::Op::Subgroup2DBlockLoadINTEL: result = Id(); resultType = Id(); break;
@@ -15222,6 +15498,8 @@ OpDecoder::OpDecoder(const ConstIter &it)
case rdcspv::Op::SpecConstantArchitectureINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::SpecConstantCapabilitiesINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::ConditionalCopyObjectINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::PredicatedLoadINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::PredicatedStoreINTEL: result = Id(); resultType = Id(); break;
case rdcspv::Op::GroupIMulKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::GroupFMulKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::GroupBitwiseAndKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
@@ -15236,6 +15514,9 @@ OpDecoder::OpDecoder(const ConstIter &it)
case rdcspv::Op::ConvertHandleToImageINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::ConvertHandleToSamplerINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::ConvertHandleToSampledImageINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::FDot2MixAcc32VALVE: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::FDot2MixAcc16VALVE: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case rdcspv::Op::FDot4MixAcc32VALVE: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
case Op::Max: break;
}
}
@@ -15427,6 +15708,8 @@ rdcstr DoStringise(const rdcspv::Generator &el)
STRINGISE_ENUM_CLASS_NAMED(Kongruent, "Kongruent from Robert Konrad - Contact Robert Konrad, https://github.com/Kode/Kongruent");
STRINGISE_ENUM_CLASS_NAMED(NuvkSPIRVEmitterandDLSLcompiler, "Nuvk SPIR-V Emitter and DLSL compiler from Kitsunebi Games - Contact Luna Nielsen, luna@foxgirls.gay, https://github.com/Inochi2D/nuvk");
STRINGISE_ENUM_CLASS_NAMED(Arc3DShaderCompiler, "Arc3D Shader Compiler from Icyllis Milica - Contact Icyllis Milica, https://github.com/BloCamLimb/Arc3D");
STRINGISE_ENUM_CLASS_NAMED(Pred, "Pred from Isochron - Contact Justin Ead, jebrim@isochrontechnologies.com");
STRINGISE_ENUM_CLASS_NAMED(ApilaJaiCompiler, "Apila Jai Compiler from apilatosba - https://github.com/apilatosba/jai_to_spirv_compiler");
}
END_ENUM_STRINGISE();
}
renderdoc/driver/shaders/spirv/spirv_gen.h
+71 -6
View File
@@ -56,7 +56,7 @@ namespace rdcspv
static const uint32_t MagicNumber = 0x07230203;
static const uint32_t VersionMajor = 1;
static const uint32_t VersionMinor = 6;
static const uint32_t VersionRevision = 4;
static const uint32_t VersionRevision = 7;
static const uint32_t VersionPacked = (1 << 16) | (6 << 8);
static const uint32_t OpCodeMask = 0xffff;
static const uint32_t WordCountShift = 16;
@@ -119,6 +119,8 @@ enum class Generator : uint32_t
Kongruent = 44,
NuvkSPIRVEmitterandDLSLcompiler = 45,
Arc3DShaderCompiler = 49,
Pred = 50,
ApilaJaiCompiler = 51,
};
enum class ImageOperands : uint32_t
@@ -196,6 +198,7 @@ enum class LoopControl : uint32_t
NoFusionALTERA = 0x800000,
LoopCountALTERA = 0x1000000,
MaxReinvocationDelayALTERA = 0x2000000,
MultipleWaitQueuesQCOM = 0x10000000,
Max,
Invalid = ~0U,
};
@@ -279,7 +282,7 @@ enum class RayFlags : uint32_t
CullNoOpaqueKHR = 0x0080,
SkipTrianglesKHR = 0x0100,
SkipAABBsKHR = 0x0200,
ForceOpacityMicromap2StateEXT = 0x0400,
ForceOpacityMicromap2StateKHR = 0x0400,
Max,
Invalid = ~0U,
};
@@ -325,6 +328,8 @@ enum class SourceLanguage : uint32_t
Slang = 11,
Zig = 12,
Rust = 13,
Pred = 14,
ApilaJai = 15,
Max,
Invalid = ~0U,
};
@@ -441,6 +446,7 @@ enum class ExecutionMode : uint32_t
QuadDerivativesKHR = 5088,
RequireFullQuadsKHR = 5089,
SharesInputWithAMDX = 5102,
ArithmeticPoisonKHR = 5157,
OutputLinesEXT = 5269,
OutputPrimitivesEXT = 5270,
DerivativeGroupQuadsKHR = 5289,
@@ -465,6 +471,7 @@ enum class ExecutionMode : uint32_t
SchedulerTargetFmaxMhzINTEL = 5903,
MaximallyReconvergesKHR = 6023,
FPFastMathDefault = 6028,
OpacityMicromapIdKHR = 6031,
StreamingInterfaceINTEL = 6154,
RegisterMapInterfaceINTEL = 6160,
NamedBarrierCountINTEL = 6417,
@@ -704,6 +711,7 @@ enum class LinkageType : uint32_t
Export = 0,
Import = 1,
LinkOnceODR = 2,
WeakAMD = 3,
Max,
Invalid = ~0U,
};
@@ -808,6 +816,7 @@ enum class Decoration : uint32_t
PayloadDispatchIndirectAMDX = 5105,
ArrayStrideIdEXT = 5124,
OffsetIdEXT = 5125,
UTFEncodedKHR = 5145,
OverrideCoverageNV = 5248,
PassthroughNV = 5250,
ViewportRelativeNV = 5252,
@@ -1149,6 +1158,11 @@ enum class Capability : uint32_t
CooperativeMatrixLayoutsARM = 4201,
Float8EXT = 4212,
Float8CooperativeMatrixEXT = 4213,
Float6EXT = 4228,
Float4EXT = 4229,
Float8UnsignedE8M0EXT = 4230,
MXInt8EXT = 4231,
BitcastExtractEXT = 4232,
FragmentShadingRateKHR = 4422,
SubgroupBallotKHR = 4423,
DrawParameters = 4427,
@@ -1185,6 +1199,9 @@ enum class Capability : uint32_t
TileShadingQCOM = 4495,
CooperativeMatrixConversionQCOM = 4496,
TextureBlockMatch2QCOM = 4498,
MultipleWaitQueuesQCOM = 4539,
ImageGatherLinearQCOM = 4543,
ImageGatherExtendedModesQCOM = 4544,
Float16ImageAMD = 5008,
ImageGatherBiasLodAMD = 5009,
FragmentMaskAMD = 5010,
@@ -1199,7 +1216,11 @@ enum class Capability : uint32_t
BFloat16TypeKHR = 5116,
BFloat16DotProductKHR = 5117,
BFloat16CooperativeMatrixKHR = 5118,
AbortKHR = 5120,
DescriptorHeapEXT = 5128,
ConstantDataKHR = 5146,
PoisonFreezeKHR = 5156,
WeakLinkageAMD = 5181,
SampleMaskOverrideCoverageNV = 5249,
GeometryShaderPassthroughNV = 5251,
ShaderViewportIndexLayerEXT = 5254,
@@ -1241,7 +1262,7 @@ enum class Capability : uint32_t
FragmentShaderPixelInterlockEXT = 5378,
DemoteToHelperInvocation = 5379,
DisplacementMicromapNV = 5380,
RayTracingOpacityMicromapEXT = 5381,
RayTracingOpacityMicromapKHR = 5381,
ShaderInvocationReorderNV = 5383,
ShaderInvocationReorderEXT = 5388,
BindlessTextureNV = 5390,
@@ -1263,6 +1284,7 @@ enum class Capability : uint32_t
CooperativeVectorTrainingNV = 5435,
RayTracingClusterAccelerationStructureNV = 5437,
TensorAddressingNV = 5439,
CooperativeMatrixDecodeVectorNV = 5447,
SubgroupShuffleINTEL = 5568,
SubgroupBufferBlockIOINTEL = 5569,
SubgroupImageBlockIOINTEL = 5570,
@@ -1316,6 +1338,7 @@ enum class Capability : uint32_t
GroupNonUniformRotateKHR = 6026,
FloatControls2 = 6029,
FMAKHR = 6030,
RayTracingOpacityMicromapExecutionModeKHR = 6032,
AtomicFloat32AddEXT = 6033,
AtomicFloat64AddEXT = 6034,
LongCompositesINTEL = 6089,
@@ -1323,7 +1346,7 @@ enum class Capability : uint32_t
AtomicFloat16AddEXT = 6095,
DebugInfoModuleINTEL = 6114,
BFloat16ConversionINTEL = 6115,
SplitBarrierINTEL = 6141,
SplitBarrierEXT = 6141,
ArithmeticFenceEXT = 6144,
FPGAClusterAttributesV2ALTERA = 6150,
FPGAKernelAttributesv2INTEL = 6161,
@@ -1342,12 +1365,18 @@ enum class Capability : uint32_t
UntypedVariableLengthArrayINTEL = 6243,
SpecConditionalINTEL = 6245,
FunctionVariantsINTEL = 6246,
PredicatedIOINTEL = 6257,
RoundedDivideSqrtINTEL = 6265,
GroupUniformArithmeticKHR = 6400,
TensorFloat32RoundingINTEL = 6425,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
RegisterLimitsINTEL = 6460,
BindlessImagesINTEL = 6528,
DotProductFloat16AccFloat32VALVE = 6912,
DotProductFloat16AccFloat16VALVE = 6913,
DotProductBFloat16AccVALVE = 6914,
DotProductFloat8AccFloat32VALVE = 6915,
Max,
Invalid = ~0U,
};
@@ -1444,6 +1473,7 @@ enum class TensorAddressingOperands : uint32_t
None = 0x0000,
TensorView = 0x0001,
DecodeFunc = 0x0002,
DecodeVectorFunc = 0x0004,
Max,
Invalid = ~0U,
};
@@ -1514,6 +1544,11 @@ enum class FPEncoding : uint32_t
BFloat16KHR = 0,
Float8E4M3EXT = 4214,
Float8E5M2EXT = 4215,
Float6E2M3EXT = 4223,
Float6E3M2EXT = 4224,
Float4E2M1EXT = 4225,
Float8UnsignedE8M0EXT = 4226,
MXInt8EXT = 4227,
Max,
Invalid = ~0U,
};
@@ -1549,6 +1584,16 @@ enum class ComponentType : uint32_t
Invalid = ~0U,
};
enum class GatherModes : uint32_t
{
Gather4x1QCOM = 0,
GatherDQCOM = 1,
GatherH2QCOM = 2,
GatherV2QCOM = 3,
Max,
Invalid = ~0U,
};
using IdResultType = Id;
using IdResult = Id;
@@ -1650,6 +1695,7 @@ struct LoopControlAndParamDatas
uint32_t speculatedIterationsALTERA = {};
uint32_t loopCountALTERA = {};
uint32_t maxReinvocationDelayALTERA = {};
uint32_t multipleWaitQueuesQCOM = {};
operator LoopControl() const { return flags; }
bool operator &(const LoopControl v) const { return bool(flags & v); }
@@ -1693,6 +1739,8 @@ struct LoopControlAndParamDatas
void unsetLoopCountALTERA() { flags &= ~LoopControl::LoopCountALTERA; }
void setMaxReinvocationDelayALTERA(uint32_t maxReinvocationDelayALTERAParam) { flags |= LoopControl::MaxReinvocationDelayALTERA; maxReinvocationDelayALTERA = maxReinvocationDelayALTERAParam; }
void unsetMaxReinvocationDelayALTERA() { flags &= ~LoopControl::MaxReinvocationDelayALTERA; }
void setMultipleWaitQueuesQCOM(uint32_t multipleWaitQueuesQCOMParam) { flags |= LoopControl::MultipleWaitQueuesQCOM; multipleWaitQueuesQCOM = multipleWaitQueuesQCOMParam; }
void unsetMultipleWaitQueuesQCOM() { flags &= ~LoopControl::MultipleWaitQueuesQCOM; }
};
struct MemoryAccessAndParamDatas
@@ -1835,6 +1883,7 @@ struct ExecutionModeAndParamData
uint32_t numSIMDWorkitemsINTEL;
uint32_t schedulerTargetFmaxMhzINTEL;
FPFastMathDefaultParams fPFastMathDefault;
Id opacityMicromapIdKHR;
uint32_t streamingInterfaceINTEL;
uint32_t registerMapInterfaceINTEL;
uint32_t namedBarrierCountINTEL;
@@ -1980,6 +2029,7 @@ struct TensorAddressingOperandsAndParamDatas
TensorAddressingOperands flags;
Id tensorView = {};
Id decodeFunc = {};
Id decodeVectorFunc = {};
operator TensorAddressingOperands() const { return flags; }
bool operator &(const TensorAddressingOperands v) const { return bool(flags & v); }
@@ -1989,6 +2039,8 @@ struct TensorAddressingOperandsAndParamDatas
void unsetTensorView() { flags &= ~TensorAddressingOperands::TensorView; }
void setDecodeFunc(Id decodeFuncParam) { flags |= TensorAddressingOperands::DecodeFunc; decodeFunc = decodeFuncParam; }
void unsetDecodeFunc() { flags &= ~TensorAddressingOperands::DecodeFunc; }
void setDecodeVectorFunc(Id decodeVectorFuncParam) { flags |= TensorAddressingOperands::DecodeVectorFunc; decodeVectorFunc = decodeVectorFuncParam; }
void unsetDecodeVectorFunc() { flags &= ~TensorAddressingOperands::DecodeVectorFunc; }
};
struct TensorOperandsAndParamDatas
@@ -2375,6 +2427,7 @@ enum class Op : uint16_t
GraphSetOutputARM = 4185,
GraphEndARM = 4186,
TypeGraphARM = 4190,
BitcastExtractEXT = 4195,
TerminateInvocation = 4416,
TypeUntypedPointerKHR = 4417,
UntypedVariableKHR = 4418,
@@ -2432,6 +2485,7 @@ enum class Op : uint16_t
CompositeConstructCoopMatQCOM = 4540,
CompositeExtractCoopMatQCOM = 4541,
ExtractSubArrayQCOM = 4542,
ImageGatherQCOM = 4545,
GroupIAddNonUniformAMD = 5000,
GroupFAddNonUniformAMD = 5001,
GroupFMinNonUniformAMD = 5002,
@@ -2455,9 +2509,14 @@ enum class Op : uint16_t
GroupNonUniformQuadAnyKHR = 5111,
TypeBufferEXT = 5115,
BufferPointerEXT = 5119,
AbortKHR = 5121,
UntypedImageTexelPointerEXT = 5126,
MemberDecorateIdEXT = 5127,
ConstantSizeOfEXT = 5129,
ConstantDataKHR = 5147,
SpecConstantDataKHR = 5148,
PoisonKHR = 5158,
FreezeKHR = 5159,
HitObjectRecordHitMotionNV = 5249,
HitObjectRecordHitWithIndexMotionNV = 5250,
HitObjectRecordMissMotionNV = 5251,
@@ -2659,8 +2718,8 @@ enum class Op : uint16_t
CompositeConstructContinuedINTEL = 6096,
ConvertFToBF16INTEL = 6116,
ConvertBF16ToFINTEL = 6117,
ControlBarrierArriveINTEL = 6142,
ControlBarrierWaitINTEL = 6143,
ControlBarrierArriveEXT = 6142,
ControlBarrierWaitEXT = 6143,
ArithmeticFenceEXT = 6145,
SubgroupBlockPrefetchINTEL = 6221,
Subgroup2DBlockLoadINTEL = 6231,
@@ -2678,6 +2737,8 @@ enum class Op : uint16_t
SpecConstantArchitectureINTEL = 6252,
SpecConstantCapabilitiesINTEL = 6253,
ConditionalCopyObjectINTEL = 6254,
PredicatedLoadINTEL = 6258,
PredicatedStoreINTEL = 6259,
GroupIMulKHR = 6401,
GroupFMulKHR = 6402,
GroupBitwiseAndKHR = 6403,
@@ -2692,6 +2753,9 @@ enum class Op : uint16_t
ConvertHandleToImageINTEL = 6529,
ConvertHandleToSamplerINTEL = 6530,
ConvertHandleToSampledImageINTEL = 6531,
FDot2MixAcc32VALVE = 6916,
FDot2MixAcc16VALVE = 6917,
FDot4MixAcc32VALVE = 6918,
Max,
};
@@ -2897,4 +2961,5 @@ DECLARE_STRINGISE_TYPE(rdcspv::MatrixMultiplyAccumulateOperands);
DECLARE_STRINGISE_TYPE(rdcspv::FPEncoding);
DECLARE_STRINGISE_TYPE(rdcspv::CooperativeVectorMatrixLayout);
DECLARE_STRINGISE_TYPE(rdcspv::ComponentType);
DECLARE_STRINGISE_TYPE(rdcspv::GatherModes);
DECLARE_STRINGISE_TYPE(rdcspv::TensorOperands);
renderdoc/driver/shaders/spirv/spirv_op_helpers.h
+487 -25
View File
@@ -380,6 +380,11 @@ inline LoopControlAndParamDatas DecodeParam(const ConstIter &it, uint32_t &word)
ret.maxReinvocationDelayALTERA = (uint32_t)it.word(word);
word += 1;
}
if(ret.flags & LoopControl::MultipleWaitQueuesQCOM)
{
ret.multipleWaitQueuesQCOM = (uint32_t)it.word(word);
word += 1;
}
return ret;
}
@@ -446,6 +451,10 @@ inline void EncodeParam(rdcarray<uint32_t> &words, const LoopControlAndParamData
{
words.push_back((uint32_t)param.maxReinvocationDelayALTERA);
}
if(param.flags & LoopControl::MultipleWaitQueuesQCOM)
{
words.push_back((uint32_t)param.multipleWaitQueuesQCOM);
}
}
inline uint16_t ExtraWordCount(const LoopControl loopControl)
@@ -467,6 +476,7 @@ inline uint16_t ExtraWordCount(const LoopControl loopControl)
case LoopControl::SpeculatedIterationsALTERA: return 1;
case LoopControl::LoopCountALTERA: return 1;
case LoopControl::MaxReinvocationDelayALTERA: return 1;
case LoopControl::MultipleWaitQueuesQCOM: return 1;
default: break;
}
return 0;
@@ -1011,6 +1021,19 @@ struct ExecutionModeParam<ExecutionMode::FPFastMathDefault>
}
};
template<>
struct ExecutionModeParam<ExecutionMode::OpacityMicromapIdKHR>
{
Id opacityMicromapIdKHR;
ExecutionModeParam(Id opacityMicromapIdKHRParam) { opacityMicromapIdKHR = opacityMicromapIdKHRParam; }
operator ExecutionModeAndParamData()
{
ExecutionModeAndParamData ret(ExecutionMode::OpacityMicromapIdKHR);
ret.opacityMicromapIdKHR = opacityMicromapIdKHR;
return ret;
}
};
template<>
struct ExecutionModeParam<ExecutionMode::StreamingInterfaceINTEL>
{
@@ -1250,6 +1273,10 @@ inline ExecutionModeAndParamData DecodeParam(const ConstIter &it, uint32_t &word
ret.fPFastMathDefault.fastMathMode = Id::fromWord(it.word(word+1));
word += 2;
break;
case ExecutionMode::OpacityMicromapIdKHR:
ret.opacityMicromapIdKHR = Id::fromWord(it.word(word));
word += 1;
break;
case ExecutionMode::StreamingInterfaceINTEL:
ret.streamingInterfaceINTEL = (uint32_t)it.word(word);
word += 1;
@@ -1401,6 +1428,9 @@ inline void EncodeParam(rdcarray<uint32_t> &words, const ExecutionModeAndParamDa
words.push_back(param.fPFastMathDefault.targetType.value());
words.push_back(param.fPFastMathDefault.fastMathMode.value());
break;
case ExecutionMode::OpacityMicromapIdKHR:
words.push_back(param.opacityMicromapIdKHR.value());
break;
case ExecutionMode::StreamingInterfaceINTEL:
words.push_back((uint32_t)param.streamingInterfaceINTEL);
break;
@@ -1460,6 +1490,7 @@ inline uint16_t ExtraWordCount(const ExecutionMode executionMode)
case ExecutionMode::NumSIMDWorkitemsINTEL: return 1;
case ExecutionMode::SchedulerTargetFmaxMhzINTEL: return 1;
case ExecutionMode::FPFastMathDefault: return 2;
case ExecutionMode::OpacityMicromapIdKHR: return 1;
case ExecutionMode::StreamingInterfaceINTEL: return 1;
case ExecutionMode::RegisterMapInterfaceINTEL: return 1;
case ExecutionMode::NamedBarrierCountINTEL: return 1;
@@ -3097,6 +3128,11 @@ inline TensorAddressingOperandsAndParamDatas DecodeParam(const ConstIter &it, ui
ret.decodeFunc = Id::fromWord(it.word(word));
word += 1;
}
if(ret.flags & TensorAddressingOperands::DecodeVectorFunc)
{
ret.decodeVectorFunc = Id::fromWord(it.word(word));
word += 1;
}
return ret;
}
@@ -3111,6 +3147,10 @@ inline void EncodeParam(rdcarray<uint32_t> &words, const TensorAddressingOperand
{
words.push_back(param.decodeFunc.value());
}
if(param.flags & TensorAddressingOperands::DecodeVectorFunc)
{
words.push_back(param.decodeVectorFunc.value());
}
}
inline uint16_t ExtraWordCount(const TensorAddressingOperands tensorAddressingOperands)
@@ -3119,6 +3159,7 @@ inline uint16_t ExtraWordCount(const TensorAddressingOperands tensorAddressingOp
{
case TensorAddressingOperands::TensorView: return 1;
case TensorAddressingOperands::DecodeFunc: return 1;
case TensorAddressingOperands::DecodeVectorFunc: return 1;
default: break;
}
return 0;
@@ -3140,6 +3181,8 @@ inline uint16_t OptionalWordCount(const CooperativeVectorMatrixLayout val) { ret
inline uint16_t OptionalWordCount(const ComponentType val) { return val != ComponentType::Invalid ? 1 : 0; }
inline uint16_t OptionalWordCount(const GatherModes val) { return val != GatherModes::Invalid ? 1 : 0; }
template<>
inline TensorOperandsAndParamDatas DecodeParam(const ConstIter &it, uint32_t &word)
{
@@ -13998,6 +14041,32 @@ struct OpTypeGraphARM
rdcarray<Id> inOutTypes;
};
struct OpBitcastExtractEXT
{
OpBitcastExtractEXT(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpBitcastExtractEXT(IdResultType resultType, IdResult result, Id base, Id offset)
: op(Op::BitcastExtractEXT)
, wordCount(FixedWordSize)
{
this->resultType = resultType;
this->result = result;
this->base = base;
this->offset = offset;
}
static constexpr Op OpCode = Op::BitcastExtractEXT;
static constexpr uint16_t FixedWordSize = 5U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
Id base;
Id offset;
};
struct OpTerminateInvocation
{
OpTerminateInvocation(const ConstIter &it)
@@ -15873,6 +15942,60 @@ struct OpExtractSubArrayQCOM
Id index;
};
struct OpImageGatherQCOM
{
OpImageGatherQCOM(const ConstIter &it)
{
uint32_t word = 0;(void)word;
this->op = OpCode;
this->wordCount = (uint16_t)it.size();
this->resultType = Id::fromWord(it.word(1));
this->result = Id::fromWord(it.word(2));
this->sampledImage = Id::fromWord(it.word(3));
this->coordinate = Id::fromWord(it.word(4));
this->component = Id::fromWord(it.word(5));
this->mode = Id::fromWord(it.word(6));
word = 7;
this->imageOperands = DecodeParam<ImageOperandsAndParamDatas>(it, word);
}
OpImageGatherQCOM(IdResultType resultType, IdResult result, Id sampledImage, Id coordinate, Id component, Id mode, ImageOperandsAndParamDatas imageOperands = ImageOperands::None)
: op(Op::ImageGatherQCOM)
, wordCount(MinWordSize + ExtraWordCount(imageOperands))
{
this->resultType = resultType;
this->result = result;
this->sampledImage = sampledImage;
this->coordinate = coordinate;
this->component = component;
this->mode = mode;
this->imageOperands = imageOperands;
}
operator Operation() const
{
rdcarray<uint32_t> words;
words.push_back(resultType.value());
words.push_back(result.value());
words.push_back(sampledImage.value());
words.push_back(coordinate.value());
words.push_back(component.value());
words.push_back(mode.value());
EncodeParam(words, imageOperands);
return Operation(OpCode, words);
}
static constexpr Op OpCode = Op::ImageGatherQCOM;
static constexpr uint16_t MinWordSize = 7U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
Id sampledImage;
Id coordinate;
Id component;
Id mode;
ImageOperandsAndParamDatas imageOperands;
};
struct OpGroupIAddNonUniformAMD
{
OpGroupIAddNonUniformAMD(const ConstIter &it)
@@ -16481,6 +16604,28 @@ struct OpBufferPointerEXT
Id buffer;
};
struct OpAbortKHR
{
OpAbortKHR(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpAbortKHR(Id messageType, Id message)
: op(Op::AbortKHR)
, wordCount(FixedWordSize)
{
this->messageType = messageType;
this->message = message;
}
static constexpr Op OpCode = Op::AbortKHR;
static constexpr uint16_t FixedWordSize = 3U;
Op op;
uint16_t wordCount;
Id messageType;
Id message;
};
struct OpUntypedImageTexelPointerEXT
{
OpUntypedImageTexelPointerEXT(const ConstIter &it)
@@ -16573,6 +16718,134 @@ struct OpConstantSizeOfEXT
Id type;
};
struct OpConstantDataKHR
{
OpConstantDataKHR(const ConstIter &it)
{
uint32_t word = 0;(void)word;
this->op = OpCode;
this->wordCount = (uint16_t)it.size();
this->resultType = Id::fromWord(it.word(1));
this->result = Id::fromWord(it.word(2));
word = 3;
this->data = MultiParam<uint32_t>(it, word);
}
OpConstantDataKHR(IdResultType resultType, IdResult result, const rdcarray<uint32_t> &data = {})
: op(Op::ConstantDataKHR)
, wordCount(MinWordSize + MultiWordCount(data))
{
this->resultType = resultType;
this->result = result;
this->data = data;
}
operator Operation() const
{
rdcarray<uint32_t> words;
words.push_back(resultType.value());
words.push_back(result.value());
for(size_t i=0; i < data.size(); i++)
{
words.push_back((uint32_t)data[i]);
}
return Operation(OpCode, words);
}
static constexpr Op OpCode = Op::ConstantDataKHR;
static constexpr uint16_t MinWordSize = 3U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
rdcarray<uint32_t> data;
};
struct OpSpecConstantDataKHR
{
OpSpecConstantDataKHR(const ConstIter &it)
{
uint32_t word = 0;(void)word;
this->op = OpCode;
this->wordCount = (uint16_t)it.size();
this->resultType = Id::fromWord(it.word(1));
this->result = Id::fromWord(it.word(2));
word = 3;
this->data = MultiParam<uint32_t>(it, word);
}
OpSpecConstantDataKHR(IdResultType resultType, IdResult result, const rdcarray<uint32_t> &data = {})
: op(Op::SpecConstantDataKHR)
, wordCount(MinWordSize + MultiWordCount(data))
{
this->resultType = resultType;
this->result = result;
this->data = data;
}
operator Operation() const
{
rdcarray<uint32_t> words;
words.push_back(resultType.value());
words.push_back(result.value());
for(size_t i=0; i < data.size(); i++)
{
words.push_back((uint32_t)data[i]);
}
return Operation(OpCode, words);
}
static constexpr Op OpCode = Op::SpecConstantDataKHR;
static constexpr uint16_t MinWordSize = 3U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
rdcarray<uint32_t> data;
};
struct OpPoisonKHR
{
OpPoisonKHR(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpPoisonKHR(IdResultType resultType, IdResult result)
: op(Op::PoisonKHR)
, wordCount(FixedWordSize)
{
this->resultType = resultType;
this->result = result;
}
static constexpr Op OpCode = Op::PoisonKHR;
static constexpr uint16_t FixedWordSize = 3U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
};
struct OpFreezeKHR
{
OpFreezeKHR(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpFreezeKHR(IdResultType resultType, IdResult result, Id value)
: op(Op::FreezeKHR)
, wordCount(FixedWordSize)
{
this->resultType = resultType;
this->result = result;
this->value = value;
}
static constexpr Op OpCode = Op::FreezeKHR;
static constexpr uint16_t FixedWordSize = 4U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
Id value;
};
struct OpHitObjectRecordHitMotionNV
{
OpHitObjectRecordHitMotionNV(const ConstIter &it)
@@ -18119,26 +18392,47 @@ struct OpHitObjectRecordFromQueryEXT
{
OpHitObjectRecordFromQueryEXT(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
uint32_t word = 0;(void)word;
this->op = OpCode;
this->wordCount = (uint16_t)it.size();
this->hitObject = Id::fromWord(it.word(1));
this->rayQuery = Id::fromWord(it.word(2));
this->sBTRecordIndex = Id::fromWord(it.word(3));
this->hitObjectAttributes = Id::fromWord(it.word(4));
this->hitKind = (it.size() > 5) ? Id::fromWord(it.word(5)) : Id();
}
OpHitObjectRecordFromQueryEXT(Id hitObject, Id rayQuery, Id sBTRecordIndex, Id hitObjectAttributes)
OpHitObjectRecordFromQueryEXT(Id hitObject, Id rayQuery, Id sBTRecordIndex, Id hitObjectAttributes, Id hitKind = Id())
: op(Op::HitObjectRecordFromQueryEXT)
, wordCount(FixedWordSize)
, wordCount(MinWordSize + OptionalWordCount(hitKind))
{
this->hitObject = hitObject;
this->rayQuery = rayQuery;
this->sBTRecordIndex = sBTRecordIndex;
this->hitObjectAttributes = hitObjectAttributes;
this->hitKind = hitKind;
}
operator Operation() const
{
rdcarray<uint32_t> words;
words.push_back(hitObject.value());
words.push_back(rayQuery.value());
words.push_back(sBTRecordIndex.value());
words.push_back(hitObjectAttributes.value());
if(hitKind != Id()) words.push_back(hitKind.value());
return Operation(OpCode, words);
}
static constexpr Op OpCode = Op::HitObjectRecordFromQueryEXT;
static constexpr uint16_t FixedWordSize = 5U;
static constexpr uint16_t MinWordSize = 5U;
Op op;
uint16_t wordCount;
Id hitObject;
Id rayQuery;
Id sBTRecordIndex;
Id hitObjectAttributes;
Id hitKind;
bool HasHitKind() const { return wordCount > 5; }
};
struct OpHitObjectRecordMissEXT
@@ -22423,24 +22717,18 @@ struct OpCompositeConstructContinuedINTEL
uint32_t word = 0;(void)word;
this->op = OpCode;
this->wordCount = (uint16_t)it.size();
this->resultType = Id::fromWord(it.word(1));
this->result = Id::fromWord(it.word(2));
word = 3;
word = 1;
this->constituents = MultiParam<Id>(it, word);
}
OpCompositeConstructContinuedINTEL(IdResultType resultType, IdResult result, const rdcarray<Id> &constituents = {})
OpCompositeConstructContinuedINTEL(const rdcarray<Id> &constituents = {})
: op(Op::CompositeConstructContinuedINTEL)
, wordCount(MinWordSize + MultiWordCount(constituents))
{
this->resultType = resultType;
this->result = result;
this->constituents = constituents;
}
operator Operation() const
{
rdcarray<uint32_t> words;
words.push_back(resultType.value());
words.push_back(result.value());
for(size_t i=0; i < constituents.size(); i++)
{
words.push_back(constituents[i].value());
@@ -22449,11 +22737,9 @@ struct OpCompositeConstructContinuedINTEL
}
static constexpr Op OpCode = Op::CompositeConstructContinuedINTEL;
static constexpr uint16_t MinWordSize = 3U;
static constexpr uint16_t MinWordSize = 1U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
rdcarray<Id> constituents;
};
@@ -22505,14 +22791,14 @@ struct OpConvertBF16ToFINTEL
Id bFloat16Value;
};
struct OpControlBarrierArriveINTEL
struct OpControlBarrierArriveEXT
{
OpControlBarrierArriveINTEL(const ConstIter &it)
OpControlBarrierArriveEXT(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpControlBarrierArriveINTEL(IdScope execution, IdScope memory, IdMemorySemantics semantics)
: op(Op::ControlBarrierArriveINTEL)
OpControlBarrierArriveEXT(IdScope execution, IdScope memory, IdMemorySemantics semantics)
: op(Op::ControlBarrierArriveEXT)
, wordCount(FixedWordSize)
{
this->execution = execution;
@@ -22520,7 +22806,7 @@ struct OpControlBarrierArriveINTEL
this->semantics = semantics;
}
static constexpr Op OpCode = Op::ControlBarrierArriveINTEL;
static constexpr Op OpCode = Op::ControlBarrierArriveEXT;
static constexpr uint16_t FixedWordSize = 4U;
Op op;
uint16_t wordCount;
@@ -22529,14 +22815,14 @@ struct OpControlBarrierArriveINTEL
IdMemorySemantics semantics;
};
struct OpControlBarrierWaitINTEL
struct OpControlBarrierWaitEXT
{
OpControlBarrierWaitINTEL(const ConstIter &it)
OpControlBarrierWaitEXT(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpControlBarrierWaitINTEL(IdScope execution, IdScope memory, IdMemorySemantics semantics)
: op(Op::ControlBarrierWaitINTEL)
OpControlBarrierWaitEXT(IdScope execution, IdScope memory, IdMemorySemantics semantics)
: op(Op::ControlBarrierWaitEXT)
, wordCount(FixedWordSize)
{
this->execution = execution;
@@ -22544,7 +22830,7 @@ struct OpControlBarrierWaitINTEL
this->semantics = semantics;
}
static constexpr Op OpCode = Op::ControlBarrierWaitINTEL;
static constexpr Op OpCode = Op::ControlBarrierWaitEXT;
static constexpr uint16_t FixedWordSize = 4U;
Op op;
uint16_t wordCount;
@@ -23176,6 +23462,98 @@ struct OpConditionalCopyObjectINTEL
rdcarray<Id> conditional_arguments;
};
struct OpPredicatedLoadINTEL
{
OpPredicatedLoadINTEL(const ConstIter &it)
{
uint32_t word = 0;(void)word;
this->op = OpCode;
this->wordCount = (uint16_t)it.size();
this->resultType = Id::fromWord(it.word(1));
this->result = Id::fromWord(it.word(2));
this->pointer = Id::fromWord(it.word(3));
this->predicate = Id::fromWord(it.word(4));
this->defaultValue = Id::fromWord(it.word(5));
word = 6;
this->memoryAccess = DecodeParam<MemoryAccessAndParamDatas>(it, word);
}
OpPredicatedLoadINTEL(IdResultType resultType, IdResult result, Id pointer, Id predicate, Id defaultValue, MemoryAccessAndParamDatas memoryAccess = MemoryAccess::None)
: op(Op::PredicatedLoadINTEL)
, wordCount(MinWordSize + ExtraWordCount(memoryAccess))
{
this->resultType = resultType;
this->result = result;
this->pointer = pointer;
this->predicate = predicate;
this->defaultValue = defaultValue;
this->memoryAccess = memoryAccess;
}
operator Operation() const
{
rdcarray<uint32_t> words;
words.push_back(resultType.value());
words.push_back(result.value());
words.push_back(pointer.value());
words.push_back(predicate.value());
words.push_back(defaultValue.value());
EncodeParam(words, memoryAccess);
return Operation(OpCode, words);
}
static constexpr Op OpCode = Op::PredicatedLoadINTEL;
static constexpr uint16_t MinWordSize = 6U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
Id pointer;
Id predicate;
Id defaultValue;
MemoryAccessAndParamDatas memoryAccess;
};
struct OpPredicatedStoreINTEL
{
OpPredicatedStoreINTEL(const ConstIter &it)
{
uint32_t word = 0;(void)word;
this->op = OpCode;
this->wordCount = (uint16_t)it.size();
this->pointer = Id::fromWord(it.word(1));
this->object = Id::fromWord(it.word(2));
this->predicate = Id::fromWord(it.word(3));
word = 4;
this->memoryAccess = DecodeParam<MemoryAccessAndParamDatas>(it, word);
}
OpPredicatedStoreINTEL(Id pointer, Id object, Id predicate, MemoryAccessAndParamDatas memoryAccess = MemoryAccess::None)
: op(Op::PredicatedStoreINTEL)
, wordCount(MinWordSize + ExtraWordCount(memoryAccess))
{
this->pointer = pointer;
this->object = object;
this->predicate = predicate;
this->memoryAccess = memoryAccess;
}
operator Operation() const
{
rdcarray<uint32_t> words;
words.push_back(pointer.value());
words.push_back(object.value());
words.push_back(predicate.value());
EncodeParam(words, memoryAccess);
return Operation(OpCode, words);
}
static constexpr Op OpCode = Op::PredicatedStoreINTEL;
static constexpr uint16_t MinWordSize = 4U;
Op op;
uint16_t wordCount;
Id pointer;
Id object;
Id predicate;
MemoryAccessAndParamDatas memoryAccess;
};
struct OpGroupIMulKHR
{
OpGroupIMulKHR(const ConstIter &it)
@@ -23552,6 +23930,90 @@ struct OpConvertHandleToSampledImageINTEL
Id operand;
};
struct OpFDot2MixAcc32VALVE
{
OpFDot2MixAcc32VALVE(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpFDot2MixAcc32VALVE(IdResultType resultType, IdResult result, Id vector1, Id vector2, Id accumulator)
: op(Op::FDot2MixAcc32VALVE)
, wordCount(FixedWordSize)
{
this->resultType = resultType;
this->result = result;
this->vector1 = vector1;
this->vector2 = vector2;
this->accumulator = accumulator;
}
static constexpr Op OpCode = Op::FDot2MixAcc32VALVE;
static constexpr uint16_t FixedWordSize = 6U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
Id vector1;
Id vector2;
Id accumulator;
};
struct OpFDot2MixAcc16VALVE
{
OpFDot2MixAcc16VALVE(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpFDot2MixAcc16VALVE(IdResultType resultType, IdResult result, Id vector1, Id vector2, Id accumulator)
: op(Op::FDot2MixAcc16VALVE)
, wordCount(FixedWordSize)
{
this->resultType = resultType;
this->result = result;
this->vector1 = vector1;
this->vector2 = vector2;
this->accumulator = accumulator;
}
static constexpr Op OpCode = Op::FDot2MixAcc16VALVE;
static constexpr uint16_t FixedWordSize = 6U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
Id vector1;
Id vector2;
Id accumulator;
};
struct OpFDot4MixAcc32VALVE
{
OpFDot4MixAcc32VALVE(const ConstIter &it)
{
memcpy(this, it.words(), sizeof(*this));
}
OpFDot4MixAcc32VALVE(IdResultType resultType, IdResult result, Id vector1, Id vector2, Id accumulator)
: op(Op::FDot4MixAcc32VALVE)
, wordCount(FixedWordSize)
{
this->resultType = resultType;
this->result = result;
this->vector1 = vector1;
this->vector2 = vector2;
this->accumulator = accumulator;
}
static constexpr Op OpCode = Op::FDot4MixAcc32VALVE;
static constexpr uint16_t FixedWordSize = 6U;
Op op;
uint16_t wordCount;
IdResultType resultType;
IdResult result;
Id vector1;
Id vector2;
Id accumulator;
};
template<typename T>
inline rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const T &el)
{
renderdoc/driver/shaders/spirv/spirv_reflect.cpp
+2
View File
@@ -1014,6 +1014,8 @@ void Reflector::MakeReflection(const GraphicsAPI sourceAPI, const ShaderStage st
case SourceLanguage::WGSL:
case SourceLanguage::Zig:
case SourceLanguage::Rust:
case SourceLanguage::Pred:
case SourceLanguage::ApilaJai:
case SourceLanguage::Max: break;
}
renderdoc/driver/shaders/spirv/spirv_registry.md
+17 -2
View File
@@ -17,7 +17,7 @@ To publish a new extension, please create a pull request which includes:
- The extension document in the asciidoc format named following
the `SPV_<vendor>_<name>.asciidoc` pattern. The document should be placed
in the `extension/<vendor>` folder.
in the `extensions/<vendor>` folder.
- README.md update with the link to the new extension once published
To publish a non-semantic extended instruction set,
@@ -37,9 +37,11 @@ Note: we no longer push the HTML along side the extension.
* [SPV_KHR_16bit_storage ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_16bit_storage.html)
* [SPV_KHR_8bit_storage ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_8bit_storage.html)
* [SPV_KHR_abort ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_abort.html)
* [SPV_KHR_bfloat16 ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_bfloat16.html)
* [SPV_KHR_bit_instructions ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_bit_instructions.html)
* [SPV_KHR_compute_shader_derivatives ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_compute_shader_derivatives.html)
* [SPV_KHR_constant_data ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_constant_data.html)
* [SPV_KHR_cooperative_matrix ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_cooperative_matrix.html)
* [SPV_KHR_device_group ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_device_group.html)
* [SPV_KHR_expect_assume ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_expect_assume.html)
@@ -54,6 +56,8 @@ Note: we no longer push the HTML along side the extension.
* [SPV_KHR_multiview ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_multiview.html)
* [SPV_KHR_no_integer_wrap_decoration ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_no_integer_wrap_decoration.html)
* [SPV_KHR_non_semantic_info ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_non_semantic_info.html)
* [SPV_KHR_opacity_micromap ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_opacity_micromap.html)
* [SPV_KHR_poison_freeze ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_poison_freeze.html)
* [SPV_KHR_physical_storage_buffer ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_physical_storage_buffer.html)
* [SPV_KHR_post_depth_coverage ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_post_depth_coverage.html)
* [SPV_KHR_quad_control ]( https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_quad_control.html)
@@ -90,6 +94,7 @@ Note: we no longer push the HTML along side the extension.
* [SPV_EXT_image_raw10_raw12 ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_image_raw10_raw12.html)
* [SPV_EXT_long_vector ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_long_vector.html)
* [SPV_EXT_mesh_shader ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_mesh_shader.html)
* [SPV_EXT_ocp_microscaling_types ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_ocp_microscaling_types.html)
* [SPV_EXT_opacity_micromap ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_opacity_micromap.html)
* [SPV_EXT_optnone ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_optnone.html)
* [SPV_EXT_physical_storage_buffer ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_physical_storage_buffer.html)
@@ -105,6 +110,7 @@ Note: we no longer push the HTML along side the extension.
* [SPV_EXT_shader_subgroup_partitioned ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_shader_subgroup_partitioned.html)
* [SPV_EXT_shader_tile_image ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_shader_tile_image.html)
* [SPV_EXT_shader_viewport_index_layer ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_shader_viewport_index_layer.html)
* [SPV_EXT_split_barrier ]( https://github.khronos.org/SPIRV-Registry/extensions/EXT/SPV_EXT_split_barrier.html)
### Vendor Extensions
@@ -139,6 +145,7 @@ Note: we no longer push the HTML along side the extension.
* [SPV_AMD_shader_image_load_store_lod ]( https://github.khronos.org/SPIRV-Registry/extensions/AMD/SPV_AMD_shader_image_load_store_lod.html)
* [SPV_AMD_shader_trinary_minmax ]( https://github.khronos.org/SPIRV-Registry/extensions/AMD/SPV_AMD_shader_trinary_minmax.html)
* [SPV_AMD_texture_gather_bias_lod ]( https://github.khronos.org/SPIRV-Registry/extensions/AMD/SPV_AMD_texture_gather_bias_lod.html)
* [SPV_AMD_weak_linkage ]( https://github.khronos.org/SPIRV-Registry/extensions/AMD/SPV_AMD_weak_linkage.html)
* [SPV_AMDX_shader_enqueue ]( https://github.khronos.org/SPIRV-Registry/extensions/AMD/SPV_AMDX_shader_enqueue.html)
* [SPV_ARM_cooperative_matrix_layouts ]( https://github.khronos.org/SPIRV-Registry/extensions/ARM/SPV_ARM_cooperative_matrix_layouts.html)
* [SPV_ARM_core_builtins ]( https://github.khronos.org/SPIRV-Registry/extensions/ARM/SPV_ARM_core_builtins.html)
@@ -162,6 +169,8 @@ Note: we no longer push the HTML along side the extension.
* [SPV_INTEL_masked_gather_scatter ]( https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_masked_gather_scatter.html)
* [SPV_INTEL_maximum_registers ]( https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_maximum_registers.html)
* [SPV_INTEL_media_block_io ]( https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_media_block_io.html)
* [SPV_INTEL_predicated_io ]( https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_predicated_io.html)
* [SPV_INTEL_rounded_divide_sqrt ]( https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_rounded_divide_sqrt.html)
* [SPV_INTEL_shader_integer_functions2 ]( https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_shader_integer_functions2.html)
* [SPV_INTEL_split_barrier ]( https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_split_barrier.html)
* [SPV_INTEL_subgroups ]( https://github.khronos.org/SPIRV-Registry/extensions/INTEL/SPV_INTEL_subgroups.html)
@@ -176,6 +185,7 @@ Note: we no longer push the HTML along side the extension.
* [SPV_NV_compute_shader_derivatives ]( https://github.khronos.org/SPIRV-Registry/extensions/NV/SPV_NV_compute_shader_derivatives.html)
* [SPV_NV_cooperative_matrix ]( https://github.khronos.org/SPIRV-Registry/extensions/NV/SPV_NV_cooperative_matrix.html)
* [SPV_NV_cooperative_matrix2 ]( https://github.khronos.org/SPIRV-Registry/extensions/NV/SPV_NV_cooperative_matrix2.html)
* [SPV_NV_cooperative_matrix_decode_vector ]( https://github.khronos.org/SPIRV-Registry/extensions/NV/SPV_NV_cooperative_matrix_decode_vector.html)
* [SPV_NV_cooperative_vector ]( https://github.khronos.org/SPIRV-Registry/extensions/NV/SPV_NV_cooperative_vector.html)
* [SPV_NV_displacement_micromap ]( https://github.khronos.org/SPIRV-Registry/extensions/NV/SPV_NV_displacement_micromap.html)
* [SPV_NV_fragment_shader_barycentric ]( https://github.khronos.org/SPIRV-Registry/extensions/NV/SPV_NV_fragment_shader_barycentric.html)
@@ -200,15 +210,20 @@ Note: we no longer push the HTML along side the extension.
* [SPV_QCOM_cooperative_matrix_conversion ]( https://github.khronos.org/SPIRV-Registry/extensions/QCOM/SPV_QCOM_cooperative_matrix_conversion.html)
* [SPV_QCOM_image_processing ]( https://github.khronos.org/SPIRV-Registry/extensions/QCOM/SPV_QCOM_image_processing.html)
* [SPV_QCOM_image_processing2 ]( https://github.khronos.org/SPIRV-Registry/extensions/QCOM/SPV_QCOM_image_processing2.html)
* [SPV_QCOM_image_processing3 ]( https://github.khronos.org/SPIRV-Registry/extensions/QCOM/SPV_QCOM_image_processing3.html)
* [SPV_QCOM_multiple_wait_queues ]( https://github.khronos.org/SPIRV-Registry/extensions/QCOM/SPV_QCOM_multiple_wait_queues.html)
* [SPV_QCOM_tile_shading ]( https://github.khronos.org/SPIRV-Registry/extensions/QCOM/SPV_QCOM_tile_shading.html)
* [SPV_VALVE_mixed_float_dot_product ]( https://github.khronos.org/SPIRV-Registry/extensions/VALVE/SPV_VALVE_mixed_float_dot_product.html)
## Non-Semantic Extended Instruction Set Specifications
* [NonSemantic.ClspvReflection ]( https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.ClspvReflection.html)
* [NonSemantic.DebugBreak ]( https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.DebugBreak.html)
* [NonSemantic.DebugPrintf ]( https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.DebugPrintf.html)
* [NonSemantic.Shader.DebugInfo.100 ]( https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.100.html)
* [NonSemantic.Graph.DebugInfo ]( https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Graph.DebugInfo.html)
* [NonSemantic.Shader.DebugInfo ]( https://github.khronos.org/SPIRV-Registry/nonsemantic/NonSemantic.Shader.DebugInfo.html)
## Extended Instruction Set Specifications
* [Arm.ExperimentalMLOperations ]( https://github.khronos.org/SPIRV-Registry/extended/Arm.ExperimentalMLOperations.html)
* [TOSA.001000.1 ]( https://github.khronos.org/SPIRV-Registry/extended/TOSA.001000.1.html)