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Assert for SPIRV Subgroup Ops that the subgroup is converged

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This commit is contained in:
Jake Turner
2025-09-24 13:49:51 +01:00
parent e5121962f3
commit 3b74e038d2
1 changed files with 5 additions and 0 deletions
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renderdoc/driver/shaders/spirv/spirv_debug.cpp
+5
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@@ -2762,6 +2762,7 @@ void ThreadState::StepNext(ShaderDebugState *state, const rdcarray<ThreadState>
if(activeMask[lane])
{
activeLanes.push_back(lane - firstLaneInSub);
RDCASSERTEQUAL(workgroup[lane - firstLaneInSub].currentInstruction, currentInstruction);
}
}
@@ -3048,6 +3049,7 @@ void ThreadState::StepNext(ShaderDebugState *state, const rdcarray<ThreadState>
lane = firstLaneInSub + uintComp(GetSrc(group.index), 0);
}
RDCASSERTEQUAL(workgroup[lane].currentInstruction, currentInstruction);
RDCASSERT(lane < workgroup.size(), lane, workgroup.size());
SetDst(opdata.result, workgroup[lane].GetSrc(value));
break;
@@ -3072,6 +3074,7 @@ void ThreadState::StepNext(ShaderDebugState *state, const rdcarray<ThreadState>
result = false;
break;
}
RDCASSERTEQUAL(workgroup[quadNeighbours[i]].currentInstruction, currentInstruction);
if(opdata.op == Op::GroupNonUniformQuadAllKHR)
result = result && workgroup[quadNeighbours[i]].GetSrc(quad.predicate).value.u32v[0];
@@ -3289,6 +3292,7 @@ void ThreadState::StepNext(ShaderDebugState *state, const rdcarray<ThreadState>
RDCASSERT(lane < workgroup.size(), lane, workgroup.size());
ShaderVariable x = workgroup[lane].GetSrc(valueId);
RDCASSERTEQUAL(workgroup[lane].currentInstruction, currentInstruction);
switch(opdata.op)
{
@@ -3486,6 +3490,7 @@ void ThreadState::StepNext(ShaderDebugState *state, const rdcarray<ThreadState>
uint32_t bit = 1U << ((lane - firstLaneInSub) % 32U);
RDCASSERT(lane < workgroup.size(), lane, workgroup.size());
RDCASSERTEQUAL(workgroup[lane].currentInstruction, currentInstruction);
ShaderVariable x = workgroup[lane].GetSrc(valueId);
if(x.value.u32v[0])