mirror of
https://github.com/baldurk/renderdoc.git
synced 2026-05-12 13:00:32 +00:00
Update SPIR-V headers to latest
This commit is contained in:
baldurk
@@ -1,6 +1,6 @@
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{
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"copyright" : [
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"Copyright (c) 2014-2016 The Khronos Group Inc.",
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"Copyright (c) 2014-2024 The Khronos Group Inc.",
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"",
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"Permission is hereby granted, free of charge, to any person obtaining a copy",
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"of this software and/or associated documentation files (the \"Materials\"),",
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+1
-1
@@ -1,6 +1,6 @@
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{
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"copyright" : [
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"Copyright (c) 2018 The Khronos Group Inc.",
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"Copyright (c) 2018-2024 The Khronos Group Inc.",
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"",
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"Permission is hereby granted, free of charge, to any person obtaining a copy",
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"of this software and/or associated documentation files (the \"Materials\"),",
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@@ -369,10 +369,18 @@ rdcstr DoStringise(const rdcspv::{name} &el)
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elif operand_kind['category'] == 'BitEnum':
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operand_kind['size'] = 1
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operand_kind['def_name'] = name[0].lower() + name[1:]
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operand_kind['def_value'] = name + '::None'
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operand_kind['type'] = name
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used = []
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none = [v['enumerant'] for v in operand_kind['enumerants'] if 'None' in v['enumerant']]
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if len(none) > 0:
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none = none[0]
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else:
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none = 'NoDefValueAvailable'
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operand_kind['def_value'] = name + '::' + none
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decl = ''
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stringise = ''
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@@ -384,8 +392,8 @@ rdcstr DoStringise(const rdcspv::{name} &el)
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used.append(value['value'])
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if value['enumerant'] == 'None':
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stringise += ' STRINGISE_BITFIELD_CLASS_VALUE(None);\n\n'
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if value['enumerant'] == none:
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stringise += ' STRINGISE_BITFIELD_CLASS_VALUE({});\n\n'.format(none)
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else:
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stringise += ' STRINGISE_BITFIELD_CLASS_BIT({});\n'.format(value['enumerant'])
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@@ -438,6 +446,11 @@ rdcstr DoStringise(const rdcspv::{name} &el)
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operand_kind['def_name'] = 'num'
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operand_kind['def_value'] = '0'
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operand_kind['type'] = 'uint32_t'
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elif (operand_kind['kind'] == 'LiteralFloat'):
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operand_kind['size'] = 1
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operand_kind['def_name'] = 'flt'
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operand_kind['def_value'] = '0.0f'
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operand_kind['type'] = 'float'
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elif (operand_kind['kind'] == 'LiteralString'):
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operand_kind['size'] = -1000000
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operand_kind['type'] = 'rdcstr'
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@@ -504,6 +517,10 @@ for operand_kind in spirv['operand_kinds']:
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if not operand_kind['has_params']:
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if operand_kind['category'] == 'ValueEnum':
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ops_header.write('inline uint16_t OptionalWordCount(const {0} val) {{ return val != {0}::Invalid ? 1 : 0; }}\n\n'.format(name))
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elif operand_kind['category'] == 'BitEnum':
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none = [v['enumerant'] for v in operand_kind['enumerants'] if 'None' in v['enumerant']]
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if len(none) > 0:
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ops_header.write('inline uint16_t OptionalWordCount(const {0} val) {{ return val != {0}::{1} ? 1 : 0; }}\n\n'.format(name, none[0]))
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continue
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values = ''
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@@ -1,7 +1,7 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<registry>
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<!--
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Copyright (c) 2015 The Khronos Group Inc.
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Copyright (c) 2015-2024 The Khronos Group Inc.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and/or associated documentation files (the
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@@ -89,7 +89,10 @@
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<id value="36" vendor="Taichi Graphics" tool="Taichi" comment="Contact Rendong Liang rendongliang@taichi.graphics, Repo https://github.com/taichi-dev/taichi"/>
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<id value="37" vendor="heroseh" tool="Hero C Compiler" comment="https://github.com/heroseh/hcc"/>
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<id value="38" vendor="Meta" tool="SparkSL" comment="Contact Dunfan Lu, dunfanlu@meta.com, https://sparkar.facebook.com/ar-studio/learn/sparksl/sparksl-overview"/>
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<unused start="39" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
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<id value="39" vendor="SirLynix" tool="Nazara ShaderLang Compiler" comment="Contact Jérôme Leclercq, https://github.com/NazaraEngine/ShaderLang"/>
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<id value="40" vendor="NVIDIA" tool="Slang Compiler" comment="Contact Theresa Foley, tfoley@nvidia.com, https://github.com/shader-slang/slang/"/>
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<id value="41" vendor="Zig Software Foundation" tool="Zig Compiler" comment="Contact Robin Voetter, https://github.com/Snektron"/>
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<unused start="42" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/>
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</ids>
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<!-- SECTION: SPIR-V Opcodes and Enumerants -->
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@@ -246,7 +249,8 @@
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<!-- Reserved FP fast math mode bits -->
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<ids type="FPFastMathMode" start="0" end="15" vendor="Khronos" comment="Reserved FPFastMathMode bits, not available to vendors - see the SPIR-V Specification"/>
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<ids type="FPFastMathMode" start="16" end="17" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
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<ids type="FPFastMathMode" start="18" end="31" comment="Unreserved bits reservable for use by vendors"/>
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<ids type="FPFastMathMode" start="18" end="18" vendor="khronos" comment="Reserved FPFastMathMode bit, not available to vendors - see SPV_KHR_float_controls2"/>
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<ids type="FPFastMathMode" start="19" end="31" comment="Unreserved bits reservable for use by vendors"/>
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<!-- SECTION: SPIR-V Memory Operand Bit Reservations -->
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File diff suppressed because it is too large
Load Diff
@@ -3796,6 +3796,25 @@ void ThreadState::StepNext(ShaderDebugState *state, const rdcarray<ThreadState>
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case Op::RayQueryGetIntersectionTriangleVertexPositionsKHR:
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case Op::ConvertBF16ToFINTEL:
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case Op::ConvertFToBF16INTEL:
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case Op::TypeCooperativeMatrixKHR:
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case Op::CooperativeMatrixLoadKHR:
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case Op::CooperativeMatrixStoreKHR:
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case Op::CooperativeMatrixMulAddKHR:
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case Op::CooperativeMatrixLengthKHR:
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case Op::ImageBlockMatchWindowSSDQCOM:
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case Op::ImageBlockMatchWindowSADQCOM:
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case Op::ImageBlockMatchGatherSSDQCOM:
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case Op::ImageBlockMatchGatherSADQCOM:
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case Op::FinalizeNodePayloadsAMDX:
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case Op::FinishWritingNodePayloadAMDX:
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case Op::InitializeNodePayloadsAMDX:
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case Op::GroupNonUniformQuadAllKHR:
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case Op::GroupNonUniformQuadAnyKHR:
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case Op::FetchMicroTriangleVertexBarycentricNV:
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case Op::FetchMicroTriangleVertexPositionNV:
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case Op::CompositeConstructContinuedINTEL:
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case Op::MaskedGatherINTEL:
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case Op::MaskedScatterINTEL:
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{
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RDCERR("Unsupported extension opcode used %s", ToStr(opdata.op).c_str());
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@@ -721,7 +721,7 @@ void Reflector::CheckDebuggable(bool &debuggable, rdcstr &debugStatus) const
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case Capability::FPGABufferLocationINTEL:
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case Capability::USMStorageClassesINTEL:
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case Capability::IOPipesINTEL:
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case Capability::LongConstantCompositeINTEL:
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case Capability::LongCompositesINTEL:
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case Capability::DebugInfoModuleINTEL:
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case Capability::BindlessTextureNV:
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case Capability::MemoryAccessAliasingINTEL:
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@@ -743,6 +743,21 @@ void Reflector::CheckDebuggable(bool &debuggable, rdcstr &debugStatus) const
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case Capability::FPGAKernelAttributesv2INTEL:
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case Capability::FPGALatencyControlINTEL:
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case Capability::FPGAArgumentInterfacesINTEL:
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case Capability::TextureBlockMatch2QCOM:
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case Capability::ShaderEnqueueAMDX:
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case Capability::QuadControlKHR:
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case Capability::DisplacementMicromapNV:
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case Capability::AtomicFloat16VectorNV:
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case Capability::RayTracingDisplacementMicromapNV:
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case Capability::CooperativeMatrixKHR:
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case Capability::FloatControls2:
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case Capability::FPGAClusterAttributesV2INTEL:
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case Capability::FPMaxErrorINTEL:
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case Capability::GlobalVariableFPGADecorationsINTEL:
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case Capability::MaskedGatherScatterINTEL:
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case Capability::CacheControlsINTEL:
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case Capability::RegisterLimitsINTEL:
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case Capability::GlobalVariableHostAccessINTEL:
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case Capability::Max:
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case Capability::Invalid:
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{
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@@ -25,7 +25,7 @@
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/******************************************************************************
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* Generated from Khronos SPIR-V machine-readable JSON grammar.
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*
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* Copyright (c) 2014-2020 The Khronos Group Inc.
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* Copyright (c) 2014-2024 The Khronos Group Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and/or associated documentation files (the "Materials"),
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@@ -101,8 +101,9 @@ rdcstr DoStringise(const rdcspv::FPFastMathMode &el)
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STRINGISE_BITFIELD_CLASS_BIT(NSZ);
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STRINGISE_BITFIELD_CLASS_BIT(AllowRecip);
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STRINGISE_BITFIELD_CLASS_BIT(Fast);
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STRINGISE_BITFIELD_CLASS_BIT(AllowContractFastINTEL);
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STRINGISE_BITFIELD_CLASS_BIT(AllowReassocINTEL);
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STRINGISE_BITFIELD_CLASS_BIT(AllowContract);
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STRINGISE_BITFIELD_CLASS_BIT(AllowReassoc);
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STRINGISE_BITFIELD_CLASS_BIT(AllowTransform);
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}
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END_BITFIELD_STRINGISE();
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}
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@@ -226,7 +227,8 @@ rdcstr DoStringise(const rdcspv::RayFlags &el)
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{
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BEGIN_BITFIELD_STRINGISE(rdcspv::RayFlags);
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{
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STRINGISE_BITFIELD_CLASS_BIT(NoneKHR);
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STRINGISE_BITFIELD_CLASS_VALUE(NoneKHR);
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STRINGISE_BITFIELD_CLASS_BIT(OpaqueKHR);
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STRINGISE_BITFIELD_CLASS_BIT(NoOpaqueKHR);
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STRINGISE_BITFIELD_CLASS_BIT(TerminateOnFirstHitKHR);
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@@ -269,6 +271,10 @@ rdcstr DoStringise(const rdcspv::SourceLanguage &el)
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STRINGISE_ENUM_CLASS(CPP_for_OpenCL);
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STRINGISE_ENUM_CLASS(SYCL);
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STRINGISE_ENUM_CLASS(HERO_C);
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STRINGISE_ENUM_CLASS(NZSL);
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STRINGISE_ENUM_CLASS(WGSL);
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STRINGISE_ENUM_CLASS(Slang);
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STRINGISE_ENUM_CLASS(Zig);
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}
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END_ENUM_STRINGISE();
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}
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@@ -378,12 +384,19 @@ rdcstr DoStringise(const rdcspv::ExecutionMode &el)
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STRINGISE_ENUM_CLASS(RoundingModeRTZ);
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STRINGISE_ENUM_CLASS(EarlyAndLateFragmentTestsAMD);
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STRINGISE_ENUM_CLASS(StencilRefReplacingEXT);
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STRINGISE_ENUM_CLASS(CoalescingAMDX);
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STRINGISE_ENUM_CLASS(MaxNodeRecursionAMDX);
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STRINGISE_ENUM_CLASS(StaticNumWorkgroupsAMDX);
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STRINGISE_ENUM_CLASS(ShaderIndexAMDX);
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STRINGISE_ENUM_CLASS(MaxNumWorkgroupsAMDX);
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STRINGISE_ENUM_CLASS(StencilRefUnchangedFrontAMD);
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STRINGISE_ENUM_CLASS(StencilRefGreaterFrontAMD);
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STRINGISE_ENUM_CLASS(StencilRefLessFrontAMD);
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STRINGISE_ENUM_CLASS(StencilRefUnchangedBackAMD);
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STRINGISE_ENUM_CLASS(StencilRefGreaterBackAMD);
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STRINGISE_ENUM_CLASS(StencilRefLessBackAMD);
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STRINGISE_ENUM_CLASS(QuadDerivativesKHR);
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STRINGISE_ENUM_CLASS(RequireFullQuadsKHR);
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STRINGISE_ENUM_CLASS(OutputLinesEXT);
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STRINGISE_ENUM_CLASS(OutputPrimitivesEXT);
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STRINGISE_ENUM_CLASS(DerivativeGroupQuadsNV);
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@@ -405,9 +418,14 @@ rdcstr DoStringise(const rdcspv::ExecutionMode &el)
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STRINGISE_ENUM_CLASS(NoGlobalOffsetINTEL);
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STRINGISE_ENUM_CLASS(NumSIMDWorkitemsINTEL);
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STRINGISE_ENUM_CLASS(SchedulerTargetFmaxMhzINTEL);
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STRINGISE_ENUM_CLASS(MaximallyReconvergesKHR);
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STRINGISE_ENUM_CLASS(FPFastMathDefault);
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STRINGISE_ENUM_CLASS(StreamingInterfaceINTEL);
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STRINGISE_ENUM_CLASS(RegisterMapInterfaceINTEL);
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STRINGISE_ENUM_CLASS(NamedBarrierCountINTEL);
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STRINGISE_ENUM_CLASS(MaximumRegistersINTEL);
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STRINGISE_ENUM_CLASS(MaximumRegistersIdINTEL);
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STRINGISE_ENUM_CLASS(NamedMaximumRegistersINTEL);
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}
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END_ENUM_STRINGISE();
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}
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@@ -431,6 +449,8 @@ rdcstr DoStringise(const rdcspv::StorageClass &el)
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STRINGISE_ENUM_CLASS(Image);
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STRINGISE_ENUM_CLASS(StorageBuffer);
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STRINGISE_ENUM_CLASS(TileImageEXT);
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STRINGISE_ENUM_CLASS(NodePayloadAMDX);
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STRINGISE_ENUM_CLASS(NodeOutputPayloadAMDX);
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STRINGISE_ENUM_CLASS(CallableDataKHR);
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STRINGISE_ENUM_CLASS(IncomingCallableDataKHR);
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STRINGISE_ENUM_CLASS(RayPayloadKHR);
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@@ -591,6 +611,8 @@ rdcstr DoStringise(const rdcspv::ImageChannelDataType &el)
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STRINGISE_ENUM_CLASS(Float);
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STRINGISE_ENUM_CLASS(UnormInt24);
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STRINGISE_ENUM_CLASS(UnormInt101010_2);
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STRINGISE_ENUM_CLASS(UnsignedIntRaw10EXT);
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STRINGISE_ENUM_CLASS(UnsignedIntRaw12EXT);
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}
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END_ENUM_STRINGISE();
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}
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@@ -684,6 +706,19 @@ rdcstr DoStringise(const rdcspv::AccessQualifier &el)
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END_ENUM_STRINGISE();
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}
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template <>
|
||||
rdcstr DoStringise(const rdcspv::HostAccessQualifier &el)
|
||||
{
|
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BEGIN_ENUM_STRINGISE(rdcspv::HostAccessQualifier);
|
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{
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STRINGISE_ENUM_CLASS(NoneINTEL);
|
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STRINGISE_ENUM_CLASS(ReadINTEL);
|
||||
STRINGISE_ENUM_CLASS(WriteINTEL);
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STRINGISE_ENUM_CLASS(ReadWriteINTEL);
|
||||
}
|
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END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::FunctionParameterAttribute &el)
|
||||
{
|
||||
@@ -758,7 +793,12 @@ rdcstr DoStringise(const rdcspv::Decoration &el)
|
||||
STRINGISE_ENUM_CLASS(NoUnsignedWrap);
|
||||
STRINGISE_ENUM_CLASS(WeightTextureQCOM);
|
||||
STRINGISE_ENUM_CLASS(BlockMatchTextureQCOM);
|
||||
STRINGISE_ENUM_CLASS(BlockMatchSamplerQCOM);
|
||||
STRINGISE_ENUM_CLASS(ExplicitInterpAMD);
|
||||
STRINGISE_ENUM_CLASS(NodeSharesPayloadLimitsWithAMDX);
|
||||
STRINGISE_ENUM_CLASS(NodeMaxPayloadsAMDX);
|
||||
STRINGISE_ENUM_CLASS(TrackFinishWritingAMDX);
|
||||
STRINGISE_ENUM_CLASS(PayloadNodeNameAMDX);
|
||||
STRINGISE_ENUM_CLASS(OverrideCoverageNV);
|
||||
STRINGISE_ENUM_CLASS(PassthroughNV);
|
||||
STRINGISE_ENUM_CLASS(ViewportRelativeNV);
|
||||
@@ -801,6 +841,9 @@ rdcstr DoStringise(const rdcspv::Decoration &el)
|
||||
STRINGISE_ENUM_CLASS(MergeINTEL);
|
||||
STRINGISE_ENUM_CLASS(BankBitsINTEL);
|
||||
STRINGISE_ENUM_CLASS(ForcePow2DepthINTEL);
|
||||
STRINGISE_ENUM_CLASS(StridesizeINTEL);
|
||||
STRINGISE_ENUM_CLASS(WordsizeINTEL);
|
||||
STRINGISE_ENUM_CLASS(TrueDualPortINTEL);
|
||||
STRINGISE_ENUM_CLASS(BurstCoalesceINTEL);
|
||||
STRINGISE_ENUM_CLASS(CacheSizeINTEL);
|
||||
STRINGISE_ENUM_CLASS(DontStaticallyCoalesceINTEL);
|
||||
@@ -819,6 +862,8 @@ rdcstr DoStringise(const rdcspv::Decoration &el)
|
||||
STRINGISE_ENUM_CLASS(SingleElementVectorINTEL);
|
||||
STRINGISE_ENUM_CLASS(VectorComputeCallableFunctionINTEL);
|
||||
STRINGISE_ENUM_CLASS(MediaBlockIOINTEL);
|
||||
STRINGISE_ENUM_CLASS(StallFreeINTEL);
|
||||
STRINGISE_ENUM_CLASS(FPMaxErrorDecorationINTEL);
|
||||
STRINGISE_ENUM_CLASS(LatencyControlLabelINTEL);
|
||||
STRINGISE_ENUM_CLASS(LatencyControlConstraintINTEL);
|
||||
STRINGISE_ENUM_CLASS(ConduitKernelArgumentINTEL);
|
||||
@@ -830,6 +875,11 @@ rdcstr DoStringise(const rdcspv::Decoration &el)
|
||||
STRINGISE_ENUM_CLASS(MMHostInterfaceMaxBurstINTEL);
|
||||
STRINGISE_ENUM_CLASS(MMHostInterfaceWaitRequestINTEL);
|
||||
STRINGISE_ENUM_CLASS(StableKernelArgumentINTEL);
|
||||
STRINGISE_ENUM_CLASS(HostAccessINTEL);
|
||||
STRINGISE_ENUM_CLASS(InitModeINTEL);
|
||||
STRINGISE_ENUM_CLASS(ImplementInRegisterMapINTEL);
|
||||
STRINGISE_ENUM_CLASS(CacheControlLoadINTEL);
|
||||
STRINGISE_ENUM_CLASS(CacheControlStoreINTEL);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
@@ -904,6 +954,8 @@ rdcstr DoStringise(const rdcspv::BuiltIn &el)
|
||||
STRINGISE_ENUM_CLASS(BaryCoordSmoothSampleAMD);
|
||||
STRINGISE_ENUM_CLASS(BaryCoordPullModelAMD);
|
||||
STRINGISE_ENUM_CLASS(FragStencilRefEXT);
|
||||
STRINGISE_ENUM_CLASS(CoalescedInputCountAMDX);
|
||||
STRINGISE_ENUM_CLASS(ShaderIndexAMDX);
|
||||
STRINGISE_ENUM_CLASS(ViewportMaskNV);
|
||||
STRINGISE_ENUM_CLASS(SecondaryPositionNV);
|
||||
STRINGISE_ENUM_CLASS(SecondaryViewportMaskNV);
|
||||
@@ -941,12 +993,16 @@ rdcstr DoStringise(const rdcspv::BuiltIn &el)
|
||||
STRINGISE_ENUM_CLASS(HitKindKHR);
|
||||
STRINGISE_ENUM_CLASS(CurrentRayTimeNV);
|
||||
STRINGISE_ENUM_CLASS(HitTriangleVertexPositionsKHR);
|
||||
STRINGISE_ENUM_CLASS(HitMicroTriangleVertexPositionsNV);
|
||||
STRINGISE_ENUM_CLASS(HitMicroTriangleVertexBarycentricsNV);
|
||||
STRINGISE_ENUM_CLASS(IncomingRayFlagsKHR);
|
||||
STRINGISE_ENUM_CLASS(RayGeometryIndexKHR);
|
||||
STRINGISE_ENUM_CLASS(WarpsPerSMNV);
|
||||
STRINGISE_ENUM_CLASS(SMCountNV);
|
||||
STRINGISE_ENUM_CLASS(WarpIDNV);
|
||||
STRINGISE_ENUM_CLASS(SMIDNV);
|
||||
STRINGISE_ENUM_CLASS(HitKindFrontFacingMicroTriangleNV);
|
||||
STRINGISE_ENUM_CLASS(HitKindBackFacingMicroTriangleNV);
|
||||
STRINGISE_ENUM_CLASS(CullMaskKHR);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
@@ -1107,6 +1163,7 @@ rdcstr DoStringise(const rdcspv::Capability &el)
|
||||
STRINGISE_ENUM_CLASS(TextureSampleWeightedQCOM);
|
||||
STRINGISE_ENUM_CLASS(TextureBoxFilterQCOM);
|
||||
STRINGISE_ENUM_CLASS(TextureBlockMatchQCOM);
|
||||
STRINGISE_ENUM_CLASS(TextureBlockMatch2QCOM);
|
||||
STRINGISE_ENUM_CLASS(Float16ImageAMD);
|
||||
STRINGISE_ENUM_CLASS(ImageGatherBiasLodAMD);
|
||||
STRINGISE_ENUM_CLASS(FragmentMaskAMD);
|
||||
@@ -1114,6 +1171,8 @@ rdcstr DoStringise(const rdcspv::Capability &el)
|
||||
STRINGISE_ENUM_CLASS(ImageReadWriteLodAMD);
|
||||
STRINGISE_ENUM_CLASS(Int64ImageEXT);
|
||||
STRINGISE_ENUM_CLASS(ShaderClockKHR);
|
||||
STRINGISE_ENUM_CLASS(ShaderEnqueueAMDX);
|
||||
STRINGISE_ENUM_CLASS(QuadControlKHR);
|
||||
STRINGISE_ENUM_CLASS(SampleMaskOverrideCoverageNV);
|
||||
STRINGISE_ENUM_CLASS(GeometryShaderPassthroughNV);
|
||||
STRINGISE_ENUM_CLASS(ShaderViewportIndexLayerEXT);
|
||||
@@ -1146,16 +1205,18 @@ rdcstr DoStringise(const rdcspv::Capability &el)
|
||||
STRINGISE_ENUM_CLASS(PhysicalStorageBufferAddresses);
|
||||
STRINGISE_ENUM_CLASS(ComputeDerivativeGroupLinearNV);
|
||||
STRINGISE_ENUM_CLASS(RayTracingProvisionalKHR);
|
||||
STRINGISE_ENUM_CLASS(CooperativeMatrixNV);
|
||||
STRINGISE_ENUM_CLASS(FragmentShaderSampleInterlockEXT);
|
||||
STRINGISE_ENUM_CLASS(FragmentShaderShadingRateInterlockEXT);
|
||||
STRINGISE_ENUM_CLASS(ShaderSMBuiltinsNV);
|
||||
STRINGISE_ENUM_CLASS(FragmentShaderPixelInterlockEXT);
|
||||
STRINGISE_ENUM_CLASS(DemoteToHelperInvocation);
|
||||
STRINGISE_ENUM_CLASS(DisplacementMicromapNV);
|
||||
STRINGISE_ENUM_CLASS(RayTracingOpacityMicromapEXT);
|
||||
STRINGISE_ENUM_CLASS(ShaderInvocationReorderNV);
|
||||
STRINGISE_ENUM_CLASS(BindlessTextureNV);
|
||||
STRINGISE_ENUM_CLASS(RayQueryPositionFetchKHR);
|
||||
STRINGISE_ENUM_CLASS(AtomicFloat16VectorNV);
|
||||
STRINGISE_ENUM_CLASS(RayTracingDisplacementMicromapNV);
|
||||
STRINGISE_ENUM_CLASS(SubgroupShuffleINTEL);
|
||||
STRINGISE_ENUM_CLASS(SubgroupBufferBlockIOINTEL);
|
||||
STRINGISE_ENUM_CLASS(SubgroupImageBlockIOINTEL);
|
||||
@@ -1203,20 +1264,29 @@ rdcstr DoStringise(const rdcspv::Capability &el)
|
||||
STRINGISE_ENUM_CLASS(DotProductInput4x8BitPacked);
|
||||
STRINGISE_ENUM_CLASS(DotProduct);
|
||||
STRINGISE_ENUM_CLASS(RayCullMaskKHR);
|
||||
STRINGISE_ENUM_CLASS(CooperativeMatrixKHR);
|
||||
STRINGISE_ENUM_CLASS(BitInstructions);
|
||||
STRINGISE_ENUM_CLASS(GroupNonUniformRotateKHR);
|
||||
STRINGISE_ENUM_CLASS(FloatControls2);
|
||||
STRINGISE_ENUM_CLASS(AtomicFloat32AddEXT);
|
||||
STRINGISE_ENUM_CLASS(AtomicFloat64AddEXT);
|
||||
STRINGISE_ENUM_CLASS(LongConstantCompositeINTEL);
|
||||
STRINGISE_ENUM_CLASS(LongCompositesINTEL);
|
||||
STRINGISE_ENUM_CLASS(OptNoneINTEL);
|
||||
STRINGISE_ENUM_CLASS(AtomicFloat16AddEXT);
|
||||
STRINGISE_ENUM_CLASS(DebugInfoModuleINTEL);
|
||||
STRINGISE_ENUM_CLASS(BFloat16ConversionINTEL);
|
||||
STRINGISE_ENUM_CLASS(SplitBarrierINTEL);
|
||||
STRINGISE_ENUM_CLASS(FPGAClusterAttributesV2INTEL);
|
||||
STRINGISE_ENUM_CLASS(FPGAKernelAttributesv2INTEL);
|
||||
STRINGISE_ENUM_CLASS(FPMaxErrorINTEL);
|
||||
STRINGISE_ENUM_CLASS(FPGALatencyControlINTEL);
|
||||
STRINGISE_ENUM_CLASS(FPGAArgumentInterfacesINTEL);
|
||||
STRINGISE_ENUM_CLASS(GlobalVariableHostAccessINTEL);
|
||||
STRINGISE_ENUM_CLASS(GlobalVariableFPGADecorationsINTEL);
|
||||
STRINGISE_ENUM_CLASS(GroupUniformArithmeticKHR);
|
||||
STRINGISE_ENUM_CLASS(MaskedGatherScatterINTEL);
|
||||
STRINGISE_ENUM_CLASS(CacheControlsINTEL);
|
||||
STRINGISE_ENUM_CLASS(RegisterLimitsINTEL);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
@@ -1265,6 +1335,93 @@ rdcstr DoStringise(const rdcspv::PackedVectorFormat &el)
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::CooperativeMatrixOperands &el)
|
||||
{
|
||||
BEGIN_BITFIELD_STRINGISE(rdcspv::CooperativeMatrixOperands);
|
||||
{
|
||||
STRINGISE_BITFIELD_CLASS_VALUE(NoneKHR);
|
||||
|
||||
STRINGISE_BITFIELD_CLASS_BIT(MatrixASignedComponentsKHR);
|
||||
STRINGISE_BITFIELD_CLASS_BIT(MatrixBSignedComponentsKHR);
|
||||
STRINGISE_BITFIELD_CLASS_BIT(MatrixCSignedComponentsKHR);
|
||||
STRINGISE_BITFIELD_CLASS_BIT(MatrixResultSignedComponentsKHR);
|
||||
STRINGISE_BITFIELD_CLASS_BIT(SaturatingAccumulationKHR);
|
||||
}
|
||||
END_BITFIELD_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::CooperativeMatrixLayout &el)
|
||||
{
|
||||
BEGIN_ENUM_STRINGISE(rdcspv::CooperativeMatrixLayout);
|
||||
{
|
||||
STRINGISE_ENUM_CLASS(RowMajorKHR);
|
||||
STRINGISE_ENUM_CLASS(ColumnMajorKHR);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::CooperativeMatrixUse &el)
|
||||
{
|
||||
BEGIN_ENUM_STRINGISE(rdcspv::CooperativeMatrixUse);
|
||||
{
|
||||
STRINGISE_ENUM_CLASS(MatrixAKHR);
|
||||
STRINGISE_ENUM_CLASS(MatrixBKHR);
|
||||
STRINGISE_ENUM_CLASS(MatrixAccumulatorKHR);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::InitializationModeQualifier &el)
|
||||
{
|
||||
BEGIN_ENUM_STRINGISE(rdcspv::InitializationModeQualifier);
|
||||
{
|
||||
STRINGISE_ENUM_CLASS(InitOnDeviceReprogramINTEL);
|
||||
STRINGISE_ENUM_CLASS(InitOnDeviceResetINTEL);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::LoadCacheControl &el)
|
||||
{
|
||||
BEGIN_ENUM_STRINGISE(rdcspv::LoadCacheControl);
|
||||
{
|
||||
STRINGISE_ENUM_CLASS(UncachedINTEL);
|
||||
STRINGISE_ENUM_CLASS(CachedINTEL);
|
||||
STRINGISE_ENUM_CLASS(StreamingINTEL);
|
||||
STRINGISE_ENUM_CLASS(InvalidateAfterReadINTEL);
|
||||
STRINGISE_ENUM_CLASS(ConstCachedINTEL);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::StoreCacheControl &el)
|
||||
{
|
||||
BEGIN_ENUM_STRINGISE(rdcspv::StoreCacheControl);
|
||||
{
|
||||
STRINGISE_ENUM_CLASS(UncachedINTEL);
|
||||
STRINGISE_ENUM_CLASS(WriteThroughINTEL);
|
||||
STRINGISE_ENUM_CLASS(WriteBackINTEL);
|
||||
STRINGISE_ENUM_CLASS(StreamingINTEL);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::NamedMaximumNumberOfRegisters &el)
|
||||
{
|
||||
BEGIN_ENUM_STRINGISE(rdcspv::NamedMaximumNumberOfRegisters);
|
||||
{
|
||||
STRINGISE_ENUM_CLASS(AutoINTEL);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
template <>
|
||||
rdcstr DoStringise(const rdcspv::Op &el)
|
||||
{
|
||||
@@ -1636,6 +1793,11 @@ rdcstr DoStringise(const rdcspv::Op &el)
|
||||
STRINGISE_ENUM_CLASS(SDotAccSat);
|
||||
STRINGISE_ENUM_CLASS(UDotAccSat);
|
||||
STRINGISE_ENUM_CLASS(SUDotAccSat);
|
||||
STRINGISE_ENUM_CLASS(TypeCooperativeMatrixKHR);
|
||||
STRINGISE_ENUM_CLASS(CooperativeMatrixLoadKHR);
|
||||
STRINGISE_ENUM_CLASS(CooperativeMatrixStoreKHR);
|
||||
STRINGISE_ENUM_CLASS(CooperativeMatrixMulAddKHR);
|
||||
STRINGISE_ENUM_CLASS(CooperativeMatrixLengthKHR);
|
||||
STRINGISE_ENUM_CLASS(TypeRayQueryKHR);
|
||||
STRINGISE_ENUM_CLASS(RayQueryInitializeKHR);
|
||||
STRINGISE_ENUM_CLASS(RayQueryTerminateKHR);
|
||||
@@ -1647,6 +1809,10 @@ rdcstr DoStringise(const rdcspv::Op &el)
|
||||
STRINGISE_ENUM_CLASS(ImageBoxFilterQCOM);
|
||||
STRINGISE_ENUM_CLASS(ImageBlockMatchSSDQCOM);
|
||||
STRINGISE_ENUM_CLASS(ImageBlockMatchSADQCOM);
|
||||
STRINGISE_ENUM_CLASS(ImageBlockMatchWindowSSDQCOM);
|
||||
STRINGISE_ENUM_CLASS(ImageBlockMatchWindowSADQCOM);
|
||||
STRINGISE_ENUM_CLASS(ImageBlockMatchGatherSSDQCOM);
|
||||
STRINGISE_ENUM_CLASS(ImageBlockMatchGatherSADQCOM);
|
||||
STRINGISE_ENUM_CLASS(GroupIAddNonUniformAMD);
|
||||
STRINGISE_ENUM_CLASS(GroupFAddNonUniformAMD);
|
||||
STRINGISE_ENUM_CLASS(GroupFMinNonUniformAMD);
|
||||
@@ -1658,6 +1824,11 @@ rdcstr DoStringise(const rdcspv::Op &el)
|
||||
STRINGISE_ENUM_CLASS(FragmentMaskFetchAMD);
|
||||
STRINGISE_ENUM_CLASS(FragmentFetchAMD);
|
||||
STRINGISE_ENUM_CLASS(ReadClockKHR);
|
||||
STRINGISE_ENUM_CLASS(FinalizeNodePayloadsAMDX);
|
||||
STRINGISE_ENUM_CLASS(FinishWritingNodePayloadAMDX);
|
||||
STRINGISE_ENUM_CLASS(InitializeNodePayloadsAMDX);
|
||||
STRINGISE_ENUM_CLASS(GroupNonUniformQuadAllKHR);
|
||||
STRINGISE_ENUM_CLASS(GroupNonUniformQuadAnyKHR);
|
||||
STRINGISE_ENUM_CLASS(HitObjectRecordHitMotionNV);
|
||||
STRINGISE_ENUM_CLASS(HitObjectRecordHitWithIndexMotionNV);
|
||||
STRINGISE_ENUM_CLASS(HitObjectRecordMissMotionNV);
|
||||
@@ -1696,6 +1867,8 @@ rdcstr DoStringise(const rdcspv::Op &el)
|
||||
STRINGISE_ENUM_CLASS(SetMeshOutputsEXT);
|
||||
STRINGISE_ENUM_CLASS(GroupNonUniformPartitionNV);
|
||||
STRINGISE_ENUM_CLASS(WritePackedPrimitiveIndices4x8NV);
|
||||
STRINGISE_ENUM_CLASS(FetchMicroTriangleVertexPositionNV);
|
||||
STRINGISE_ENUM_CLASS(FetchMicroTriangleVertexBarycentricNV);
|
||||
STRINGISE_ENUM_CLASS(ReportIntersectionNV);
|
||||
STRINGISE_ENUM_CLASS(IgnoreIntersectionNV);
|
||||
STRINGISE_ENUM_CLASS(TerminateRayNV);
|
||||
@@ -1777,6 +1950,7 @@ rdcstr DoStringise(const rdcspv::Op &el)
|
||||
STRINGISE_ENUM_CLASS(TypeStructContinuedINTEL);
|
||||
STRINGISE_ENUM_CLASS(ConstantCompositeContinuedINTEL);
|
||||
STRINGISE_ENUM_CLASS(SpecConstantCompositeContinuedINTEL);
|
||||
STRINGISE_ENUM_CLASS(CompositeConstructContinuedINTEL);
|
||||
STRINGISE_ENUM_CLASS(ConvertFToBF16INTEL);
|
||||
STRINGISE_ENUM_CLASS(ConvertBF16ToFINTEL);
|
||||
STRINGISE_ENUM_CLASS(ControlBarrierArriveINTEL);
|
||||
@@ -1789,6 +1963,8 @@ rdcstr DoStringise(const rdcspv::Op &el)
|
||||
STRINGISE_ENUM_CLASS(GroupLogicalAndKHR);
|
||||
STRINGISE_ENUM_CLASS(GroupLogicalOrKHR);
|
||||
STRINGISE_ENUM_CLASS(GroupLogicalXorKHR);
|
||||
STRINGISE_ENUM_CLASS(MaskedGatherINTEL);
|
||||
STRINGISE_ENUM_CLASS(MaskedScatterINTEL);
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
@@ -1988,6 +2164,14 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
|
||||
ret += "(" + ToStr(el.roundingModeRTE) + ")"; break;
|
||||
case ExecutionMode::RoundingModeRTZ:
|
||||
ret += "(" + ToStr(el.roundingModeRTZ) + ")"; break;
|
||||
case ExecutionMode::MaxNodeRecursionAMDX:
|
||||
ret += "(" + idName(el.maxNodeRecursionAMDX) + ")"; break;
|
||||
case ExecutionMode::StaticNumWorkgroupsAMDX:
|
||||
ret += "(" + idName(el.staticNumWorkgroupsAMDX.xsize) + ", " + idName(el.staticNumWorkgroupsAMDX.ysize) + ", " + idName(el.staticNumWorkgroupsAMDX.zsize) + ")"; break;
|
||||
case ExecutionMode::ShaderIndexAMDX:
|
||||
ret += "(" + idName(el.shaderIndexAMDX) + ")"; break;
|
||||
case ExecutionMode::MaxNumWorkgroupsAMDX:
|
||||
ret += "(" + idName(el.maxNumWorkgroupsAMDX.xsize) + ", " + idName(el.maxNumWorkgroupsAMDX.ysize) + ", " + idName(el.maxNumWorkgroupsAMDX.zsize) + ")"; break;
|
||||
case ExecutionMode::OutputPrimitivesNV:
|
||||
ret += "(" + ToStr(el.outputPrimitivesNV) + ")"; break;
|
||||
case ExecutionMode::SharedLocalMemorySizeINTEL:
|
||||
@@ -2008,12 +2192,20 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
|
||||
ret += "(" + ToStr(el.numSIMDWorkitemsINTEL) + ")"; break;
|
||||
case ExecutionMode::SchedulerTargetFmaxMhzINTEL:
|
||||
ret += "(" + ToStr(el.schedulerTargetFmaxMhzINTEL) + ")"; break;
|
||||
case ExecutionMode::FPFastMathDefault:
|
||||
ret += "(" + idName(el.fPFastMathDefault.targetType) + ", " + idName(el.fPFastMathDefault.fastMathMode) + ")"; break;
|
||||
case ExecutionMode::StreamingInterfaceINTEL:
|
||||
ret += "(" + ToStr(el.streamingInterfaceINTEL) + ")"; break;
|
||||
case ExecutionMode::RegisterMapInterfaceINTEL:
|
||||
ret += "(" + ToStr(el.registerMapInterfaceINTEL) + ")"; break;
|
||||
case ExecutionMode::NamedBarrierCountINTEL:
|
||||
ret += "(" + ToStr(el.namedBarrierCountINTEL) + ")"; break;
|
||||
case ExecutionMode::MaximumRegistersINTEL:
|
||||
ret += "(" + ToStr(el.maximumRegistersINTEL) + ")"; break;
|
||||
case ExecutionMode::MaximumRegistersIdINTEL:
|
||||
ret += "(" + idName(el.maximumRegistersIdINTEL) + ")"; break;
|
||||
case ExecutionMode::NamedMaximumRegistersINTEL:
|
||||
ret += "(" + ToStr(el.namedMaximumRegistersINTEL) + ")"; break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@@ -2072,6 +2264,10 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
|
||||
ret += "(" + idName(el.alignmentId) + ")"; break;
|
||||
case Decoration::MaxByteOffsetId:
|
||||
ret += "(" + idName(el.maxByteOffsetId) + ")"; break;
|
||||
case Decoration::NodeSharesPayloadLimitsWithAMDX:
|
||||
ret += "(" + idName(el.nodeSharesPayloadLimitsWithAMDX) + ")"; break;
|
||||
case Decoration::NodeMaxPayloadsAMDX:
|
||||
ret += "(" + idName(el.nodeMaxPayloadsAMDX) + ")"; break;
|
||||
case Decoration::SecondaryViewportRelativeNV:
|
||||
ret += "(" + ToStr(el.secondaryViewportRelativeNV) + ")"; break;
|
||||
case Decoration::SIMTCallINTEL:
|
||||
@@ -2098,6 +2294,10 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
|
||||
ret += "(" + ToStr(el.bankBitsINTEL) + ")"; break;
|
||||
case Decoration::ForcePow2DepthINTEL:
|
||||
ret += "(" + ToStr(el.forcePow2DepthINTEL) + ")"; break;
|
||||
case Decoration::StridesizeINTEL:
|
||||
ret += "(" + ToStr(el.stridesizeINTEL) + ")"; break;
|
||||
case Decoration::WordsizeINTEL:
|
||||
ret += "(" + ToStr(el.wordsizeINTEL) + ")"; break;
|
||||
case Decoration::CacheSizeINTEL:
|
||||
ret += "(" + ToStr(el.cacheSizeINTEL) + ")"; break;
|
||||
case Decoration::PrefetchINTEL:
|
||||
@@ -2120,6 +2320,8 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
|
||||
ret += "(" + ToStr(el.iOPipeStorageINTEL) + ")"; break;
|
||||
case Decoration::FunctionFloatingPointModeINTEL:
|
||||
ret += "(" + ToStr(el.functionFloatingPointModeINTEL.targetWidth) + ", " + ToStr(el.functionFloatingPointModeINTEL.fPOperationMode) + ")"; break;
|
||||
case Decoration::FPMaxErrorDecorationINTEL:
|
||||
ret += "(" + ToStr(el.fPMaxErrorDecorationINTEL) + ")"; break;
|
||||
case Decoration::LatencyControlLabelINTEL:
|
||||
ret += "(" + ToStr(el.latencyControlLabelINTEL) + ")"; break;
|
||||
case Decoration::LatencyControlConstraintINTEL:
|
||||
@@ -2136,6 +2338,14 @@ rdcstr ParamToStr(const std::function<rdcstr(rdcspv::Id)> &idName, const rdcspv:
|
||||
ret += "(" + ToStr(el.mMHostInterfaceMaxBurstINTEL) + ")"; break;
|
||||
case Decoration::MMHostInterfaceWaitRequestINTEL:
|
||||
ret += "(" + ToStr(el.mMHostInterfaceWaitRequestINTEL) + ")"; break;
|
||||
case Decoration::InitModeINTEL:
|
||||
ret += "(" + ToStr(el.initModeINTEL) + ")"; break;
|
||||
case Decoration::ImplementInRegisterMapINTEL:
|
||||
ret += "(" + ToStr(el.implementInRegisterMapINTEL) + ")"; break;
|
||||
case Decoration::CacheControlLoadINTEL:
|
||||
ret += "(" + ToStr(el.cacheControlLoadINTEL.cacheLevel) + ", " + ToStr(el.cacheControlLoadINTEL.cacheControl) + ")"; break;
|
||||
case Decoration::CacheControlStoreINTEL:
|
||||
ret += "(" + ToStr(el.cacheControlStoreINTEL.cacheLevel) + ", " + ToStr(el.cacheControlStoreINTEL.cacheControl) + ")"; break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@@ -4163,6 +4373,39 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
break;
|
||||
case rdcspv::Op::TypeCooperativeMatrixKHR:
|
||||
callback(Id::fromWord(it.word(1)), true);
|
||||
callback(Id::fromWord(it.word(2)), false);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
break;
|
||||
case rdcspv::Op::CooperativeMatrixLoadKHR:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
if(5 < size) callback(Id::fromWord(it.word(5)), false);
|
||||
break;
|
||||
case rdcspv::Op::CooperativeMatrixStoreKHR:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), false);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
if(4 < size) callback(Id::fromWord(it.word(4)), false);
|
||||
break;
|
||||
case rdcspv::Op::CooperativeMatrixMulAddKHR:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
break;
|
||||
case rdcspv::Op::CooperativeMatrixLengthKHR:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
break;
|
||||
case rdcspv::Op::TypeRayQueryKHR:
|
||||
callback(Id::fromWord(it.word(1)), true);
|
||||
break;
|
||||
@@ -4229,6 +4472,42 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
callback(Id::fromWord(it.word(7)), false);
|
||||
break;
|
||||
case rdcspv::Op::ImageBlockMatchWindowSSDQCOM:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
callback(Id::fromWord(it.word(7)), false);
|
||||
break;
|
||||
case rdcspv::Op::ImageBlockMatchWindowSADQCOM:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
callback(Id::fromWord(it.word(7)), false);
|
||||
break;
|
||||
case rdcspv::Op::ImageBlockMatchGatherSSDQCOM:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
callback(Id::fromWord(it.word(7)), false);
|
||||
break;
|
||||
case rdcspv::Op::ImageBlockMatchGatherSADQCOM:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
callback(Id::fromWord(it.word(7)), false);
|
||||
break;
|
||||
case rdcspv::Op::GroupIAddNonUniformAMD:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
@@ -4295,6 +4574,30 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
break;
|
||||
case rdcspv::Op::FinalizeNodePayloadsAMDX:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
break;
|
||||
case rdcspv::Op::FinishWritingNodePayloadAMDX:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
break;
|
||||
case rdcspv::Op::InitializeNodePayloadsAMDX:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), false);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
break;
|
||||
case rdcspv::Op::GroupNonUniformQuadAllKHR:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
break;
|
||||
case rdcspv::Op::GroupNonUniformQuadAnyKHR:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
break;
|
||||
case rdcspv::Op::HitObjectRecordHitMotionNV:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), false);
|
||||
@@ -4546,6 +4849,24 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), false);
|
||||
break;
|
||||
case rdcspv::Op::FetchMicroTriangleVertexPositionNV:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
callback(Id::fromWord(it.word(7)), false);
|
||||
break;
|
||||
case rdcspv::Op::FetchMicroTriangleVertexBarycentricNV:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
callback(Id::fromWord(it.word(7)), false);
|
||||
break;
|
||||
case rdcspv::Op::ReportIntersectionNV:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
@@ -4995,6 +5316,11 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
|
||||
case rdcspv::Op::SpecConstantCompositeContinuedINTEL:
|
||||
for(size_t i=0; i < size-1; i++) callback(Id::fromWord(it.word(1+i)), false);
|
||||
break;
|
||||
case rdcspv::Op::CompositeConstructContinuedINTEL:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
for(size_t i=0; i < size-3; i++) callback(Id::fromWord(it.word(3+i)), false);
|
||||
break;
|
||||
case rdcspv::Op::ConvertFToBF16INTEL:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
@@ -5063,6 +5389,18 @@ void OpDecoder::ForEachID(const ConstIter &it, const std::function<void(Id,bool)
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
break;
|
||||
case rdcspv::Op::MaskedGatherINTEL:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), true);
|
||||
callback(Id::fromWord(it.word(3)), false);
|
||||
callback(Id::fromWord(it.word(5)), false);
|
||||
callback(Id::fromWord(it.word(6)), false);
|
||||
break;
|
||||
case rdcspv::Op::MaskedScatterINTEL:
|
||||
callback(Id::fromWord(it.word(1)), false);
|
||||
callback(Id::fromWord(it.word(2)), false);
|
||||
callback(Id::fromWord(it.word(4)), false);
|
||||
break;
|
||||
case Op::Max: break;
|
||||
}
|
||||
}
|
||||
@@ -9199,6 +9537,73 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::TypeCooperativeMatrixKHR:
|
||||
{
|
||||
OpTypeCooperativeMatrixKHR decoded(it);
|
||||
ret += idName(decoded.result) + " = ";
|
||||
ret += rdcstr("TypeCooperativeMatrixKHR("_lit)
|
||||
+ ParamToStr(idName, decoded.componentType)
|
||||
+ ", "
|
||||
+ ToStr(Scope(constIntVal(decoded.scope)))
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.rows)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.columns)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.use)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::CooperativeMatrixLoadKHR:
|
||||
{
|
||||
OpCooperativeMatrixLoadKHR decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("CooperativeMatrixLoadKHR("_lit)
|
||||
+ ParamToStr(idName, decoded.pointer)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.memoryLayout)
|
||||
+ (5 < size ? ", " + ParamToStr(idName, decoded.stride) : "")
|
||||
+ (6 < size ? ", " + ParamToStr(idName, decoded.memoryOperand) : "")
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::CooperativeMatrixStoreKHR:
|
||||
{
|
||||
OpCooperativeMatrixStoreKHR decoded(it);
|
||||
ret += rdcstr("CooperativeMatrixStoreKHR("_lit)
|
||||
+ ParamToStr(idName, decoded.pointer)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.object)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.memoryLayout)
|
||||
+ (4 < size ? ", " + ParamToStr(idName, decoded.stride) : "")
|
||||
+ (5 < size ? ", " + ParamToStr(idName, decoded.memoryOperand) : "")
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::CooperativeMatrixMulAddKHR:
|
||||
{
|
||||
OpCooperativeMatrixMulAddKHR decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("CooperativeMatrixMulAddKHR("_lit)
|
||||
+ ParamToStr(idName, decoded.a)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.b)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.c)
|
||||
+ (6 < size ? ", " + ParamToStr(idName, decoded.cooperativeMatrixOperands) : "")
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::CooperativeMatrixLengthKHR:
|
||||
{
|
||||
OpCooperativeMatrixLengthKHR decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("CooperativeMatrixLengthKHR("_lit)
|
||||
+ ParamToStr(idName, decoded.type)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::TypeRayQueryKHR:
|
||||
{
|
||||
OpTypeRayQueryKHR decoded(it);
|
||||
@@ -9335,6 +9740,74 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::ImageBlockMatchWindowSSDQCOM:
|
||||
{
|
||||
OpImageBlockMatchWindowSSDQCOM decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("ImageBlockMatchWindowSSDQCOM("_lit)
|
||||
+ ParamToStr(idName, decoded.targetSampledImage)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.targetCoordinates)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.referenceSampledImage)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.referenceCoordinates)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.blockSize)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::ImageBlockMatchWindowSADQCOM:
|
||||
{
|
||||
OpImageBlockMatchWindowSADQCOM decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("ImageBlockMatchWindowSADQCOM("_lit)
|
||||
+ ParamToStr(idName, decoded.targetSampledImage)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.targetCoordinates)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.referenceSampledImage)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.referenceCoordinates)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.blockSize)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::ImageBlockMatchGatherSSDQCOM:
|
||||
{
|
||||
OpImageBlockMatchGatherSSDQCOM decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("ImageBlockMatchGatherSSDQCOM("_lit)
|
||||
+ ParamToStr(idName, decoded.targetSampledImage)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.targetCoordinates)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.referenceSampledImage)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.referenceCoordinates)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.blockSize)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::ImageBlockMatchGatherSADQCOM:
|
||||
{
|
||||
OpImageBlockMatchGatherSADQCOM decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("ImageBlockMatchGatherSADQCOM("_lit)
|
||||
+ ParamToStr(idName, decoded.targetSampledImage)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.targetCoordinates)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.referenceSampledImage)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.referenceCoordinates)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.blockSize)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::GroupIAddNonUniformAMD:
|
||||
{
|
||||
OpGroupIAddNonUniformAMD decoded(it);
|
||||
@@ -9472,6 +9945,55 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::FinalizeNodePayloadsAMDX:
|
||||
{
|
||||
OpFinalizeNodePayloadsAMDX decoded(it);
|
||||
ret += rdcstr("FinalizeNodePayloadsAMDX("_lit)
|
||||
+ ParamToStr(idName, decoded.payloadArray)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::FinishWritingNodePayloadAMDX:
|
||||
{
|
||||
OpFinishWritingNodePayloadAMDX decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("FinishWritingNodePayloadAMDX("_lit)
|
||||
+ ParamToStr(idName, decoded.payload)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::InitializeNodePayloadsAMDX:
|
||||
{
|
||||
OpInitializeNodePayloadsAMDX decoded(it);
|
||||
ret += rdcstr("InitializeNodePayloadsAMDX("_lit)
|
||||
+ ParamToStr(idName, decoded.payloadArray)
|
||||
+ ", "
|
||||
+ ToStr(Scope(constIntVal(decoded.visibility)))
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.payloadCount)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.nodeIndex)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::GroupNonUniformQuadAllKHR:
|
||||
{
|
||||
OpGroupNonUniformQuadAllKHR decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("GroupNonUniformQuadAllKHR("_lit)
|
||||
+ ParamToStr(idName, decoded.predicate)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::GroupNonUniformQuadAnyKHR:
|
||||
{
|
||||
OpGroupNonUniformQuadAnyKHR decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("GroupNonUniformQuadAnyKHR("_lit)
|
||||
+ ParamToStr(idName, decoded.predicate)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::HitObjectRecordHitMotionNV:
|
||||
{
|
||||
OpHitObjectRecordHitMotionNV decoded(it);
|
||||
@@ -9985,6 +10507,40 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::FetchMicroTriangleVertexPositionNV:
|
||||
{
|
||||
OpFetchMicroTriangleVertexPositionNV decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("FetchMicroTriangleVertexPositionNV("_lit)
|
||||
+ ParamToStr(idName, decoded.accel)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.instanceId)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.geometryIndex)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.primitiveIndex)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.barycentric)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::FetchMicroTriangleVertexBarycentricNV:
|
||||
{
|
||||
OpFetchMicroTriangleVertexBarycentricNV decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("FetchMicroTriangleVertexBarycentricNV("_lit)
|
||||
+ ParamToStr(idName, decoded.accel)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.instanceId)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.geometryIndex)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.primitiveIndex)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.barycentric)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::ReportIntersectionNV:
|
||||
{
|
||||
OpReportIntersectionNV decoded(it);
|
||||
@@ -10892,6 +11448,15 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::CompositeConstructContinuedINTEL:
|
||||
{
|
||||
OpCompositeConstructContinuedINTEL decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("CompositeConstructContinuedINTEL("_lit)
|
||||
+ ParamsToStr(idName, decoded.constituents)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::ConvertFToBF16INTEL:
|
||||
{
|
||||
OpConvertFToBF16INTEL decoded(it);
|
||||
@@ -11038,6 +11603,35 @@ rdcstr OpDecoder::Disassemble(const ConstIter &it, const std::function<rdcstr(Id
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::MaskedGatherINTEL:
|
||||
{
|
||||
OpMaskedGatherINTEL decoded(it);
|
||||
ret += declName(decoded.resultType, decoded.result) + " = ";
|
||||
ret += rdcstr("MaskedGatherINTEL("_lit)
|
||||
+ ParamToStr(idName, decoded.ptrVector)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.alignment)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.mask)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.fillEmpty)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case rdcspv::Op::MaskedScatterINTEL:
|
||||
{
|
||||
OpMaskedScatterINTEL decoded(it);
|
||||
ret += rdcstr("MaskedScatterINTEL("_lit)
|
||||
+ ParamToStr(idName, decoded.inputVector)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.ptrVector)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.alignment)
|
||||
+ ", "
|
||||
+ ParamToStr(idName, decoded.mask)
|
||||
+ ")";
|
||||
break;
|
||||
}
|
||||
case Op::Max: break;
|
||||
}
|
||||
return ret;
|
||||
@@ -11415,6 +12009,11 @@ OpDecoder::OpDecoder(const ConstIter &it)
|
||||
case rdcspv::Op::SDotAccSat: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::UDotAccSat: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::SUDotAccSat: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::TypeCooperativeMatrixKHR: result = Id::fromWord(it.word(1)); resultType = Id(); break;
|
||||
case rdcspv::Op::CooperativeMatrixLoadKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::CooperativeMatrixStoreKHR: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::CooperativeMatrixMulAddKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::CooperativeMatrixLengthKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::TypeRayQueryKHR: result = Id::fromWord(it.word(1)); resultType = Id(); break;
|
||||
case rdcspv::Op::RayQueryInitializeKHR: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::RayQueryTerminateKHR: result = Id(); resultType = Id(); break;
|
||||
@@ -11426,6 +12025,10 @@ OpDecoder::OpDecoder(const ConstIter &it)
|
||||
case rdcspv::Op::ImageBoxFilterQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ImageBlockMatchSSDQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ImageBlockMatchSADQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ImageBlockMatchWindowSSDQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ImageBlockMatchWindowSADQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ImageBlockMatchGatherSSDQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ImageBlockMatchGatherSADQCOM: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::GroupIAddNonUniformAMD: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::GroupFAddNonUniformAMD: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::GroupFMinNonUniformAMD: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
@@ -11437,6 +12040,11 @@ OpDecoder::OpDecoder(const ConstIter &it)
|
||||
case rdcspv::Op::FragmentMaskFetchAMD: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::FragmentFetchAMD: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ReadClockKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::FinalizeNodePayloadsAMDX: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::FinishWritingNodePayloadAMDX: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::InitializeNodePayloadsAMDX: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::GroupNonUniformQuadAllKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::GroupNonUniformQuadAnyKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::HitObjectRecordHitMotionNV: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::HitObjectRecordHitWithIndexMotionNV: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::HitObjectRecordMissMotionNV: result = Id(); resultType = Id(); break;
|
||||
@@ -11475,6 +12083,8 @@ OpDecoder::OpDecoder(const ConstIter &it)
|
||||
case rdcspv::Op::SetMeshOutputsEXT: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::GroupNonUniformPartitionNV: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::WritePackedPrimitiveIndices4x8NV: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::FetchMicroTriangleVertexPositionNV: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::FetchMicroTriangleVertexBarycentricNV: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ReportIntersectionNV: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::IgnoreIntersectionNV: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::TerminateRayNV: result = Id(); resultType = Id(); break;
|
||||
@@ -11556,6 +12166,7 @@ OpDecoder::OpDecoder(const ConstIter &it)
|
||||
case rdcspv::Op::TypeStructContinuedINTEL: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::ConstantCompositeContinuedINTEL: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::SpecConstantCompositeContinuedINTEL: result = Id(); resultType = Id(); break;
|
||||
case rdcspv::Op::CompositeConstructContinuedINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ConvertFToBF16INTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ConvertBF16ToFINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::ControlBarrierArriveINTEL: result = Id(); resultType = Id(); break;
|
||||
@@ -11568,6 +12179,8 @@ OpDecoder::OpDecoder(const ConstIter &it)
|
||||
case rdcspv::Op::GroupLogicalAndKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::GroupLogicalOrKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::GroupLogicalXorKHR: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::MaskedGatherINTEL: result = Id::fromWord(it.word(2)); resultType = Id::fromWord(it.word(1)); break;
|
||||
case rdcspv::Op::MaskedScatterINTEL: result = Id(); resultType = Id(); break;
|
||||
case Op::Max: break;
|
||||
}
|
||||
}
|
||||
@@ -11751,6 +12364,9 @@ rdcstr DoStringise(const rdcspv::Generator &el)
|
||||
STRINGISE_ENUM_CLASS_NAMED(Taichi, "Taichi from Taichi Graphics - Contact Rendong Liang rendongliang@taichi.graphics, Repo https://github.com/taichi-dev/taichi");
|
||||
STRINGISE_ENUM_CLASS_NAMED(HeroCCompiler, "Hero C Compiler from heroseh - https://github.com/heroseh/hcc");
|
||||
STRINGISE_ENUM_CLASS_NAMED(SparkSL, "SparkSL from Meta - Contact Dunfan Lu, dunfanlu@meta.com, https://sparkar.facebook.com/ar-studio/learn/sparksl/sparksl-overview");
|
||||
STRINGISE_ENUM_CLASS_NAMED(NazaraShaderLangCompiler, "Nazara ShaderLang Compiler from SirLynix - Contact Jérôme Leclercq, https://github.com/NazaraEngine/ShaderLang");
|
||||
STRINGISE_ENUM_CLASS_NAMED(SlangCompiler, "Slang Compiler from NVIDIA - Contact Theresa Foley, tfoley@nvidia.com, https://github.com/shader-slang/slang/");
|
||||
STRINGISE_ENUM_CLASS_NAMED(ZigCompiler, "Zig Compiler from Zig Software Foundation - Contact Robin Voetter, https://github.com/Snektron");
|
||||
}
|
||||
END_ENUM_STRINGISE();
|
||||
}
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
/******************************************************************************
|
||||
* Generated from Khronos SPIR-V machine-readable JSON grammar.
|
||||
*
|
||||
* Copyright (c) 2014-2020 The Khronos Group Inc.
|
||||
* Copyright (c) 2014-2024 The Khronos Group Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and/or associated documentation files (the "Materials"),
|
||||
@@ -127,6 +127,9 @@ enum class Generator : uint32_t
|
||||
Taichi = 36,
|
||||
HeroCCompiler = 37,
|
||||
SparkSL = 38,
|
||||
NazaraShaderLangCompiler = 39,
|
||||
SlangCompiler = 40,
|
||||
ZigCompiler = 41,
|
||||
};
|
||||
|
||||
enum class ImageOperands : uint32_t
|
||||
@@ -166,8 +169,11 @@ enum class FPFastMathMode : uint32_t
|
||||
NSZ = 0x0004,
|
||||
AllowRecip = 0x0008,
|
||||
Fast = 0x0010,
|
||||
AllowContract = 0x10000,
|
||||
AllowContractFastINTEL = 0x10000,
|
||||
AllowReassoc = 0x20000,
|
||||
AllowReassocINTEL = 0x20000,
|
||||
AllowTransform = 0x40000,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
@@ -327,6 +333,10 @@ enum class SourceLanguage : uint32_t
|
||||
CPP_for_OpenCL = 6,
|
||||
SYCL = 7,
|
||||
HERO_C = 8,
|
||||
NZSL = 9,
|
||||
WGSL = 10,
|
||||
Slang = 11,
|
||||
Zig = 12,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
@@ -434,12 +444,19 @@ enum class ExecutionMode : uint32_t
|
||||
RoundingModeRTZ = 4463,
|
||||
EarlyAndLateFragmentTestsAMD = 5017,
|
||||
StencilRefReplacingEXT = 5027,
|
||||
CoalescingAMDX = 5069,
|
||||
MaxNodeRecursionAMDX = 5071,
|
||||
StaticNumWorkgroupsAMDX = 5072,
|
||||
ShaderIndexAMDX = 5073,
|
||||
MaxNumWorkgroupsAMDX = 5077,
|
||||
StencilRefUnchangedFrontAMD = 5079,
|
||||
StencilRefGreaterFrontAMD = 5080,
|
||||
StencilRefLessFrontAMD = 5081,
|
||||
StencilRefUnchangedBackAMD = 5082,
|
||||
StencilRefGreaterBackAMD = 5083,
|
||||
StencilRefLessBackAMD = 5084,
|
||||
QuadDerivativesKHR = 5088,
|
||||
RequireFullQuadsKHR = 5089,
|
||||
OutputLinesNV = 5269,
|
||||
OutputLinesEXT = 5269,
|
||||
OutputPrimitivesNV = 5270,
|
||||
@@ -464,9 +481,14 @@ enum class ExecutionMode : uint32_t
|
||||
NoGlobalOffsetINTEL = 5895,
|
||||
NumSIMDWorkitemsINTEL = 5896,
|
||||
SchedulerTargetFmaxMhzINTEL = 5903,
|
||||
MaximallyReconvergesKHR = 6023,
|
||||
FPFastMathDefault = 6028,
|
||||
StreamingInterfaceINTEL = 6154,
|
||||
RegisterMapInterfaceINTEL = 6160,
|
||||
NamedBarrierCountINTEL = 6417,
|
||||
MaximumRegistersINTEL = 6461,
|
||||
MaximumRegistersIdINTEL = 6462,
|
||||
NamedMaximumRegistersINTEL = 6463,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
@@ -487,6 +509,8 @@ enum class StorageClass : uint32_t
|
||||
Image = 11,
|
||||
StorageBuffer = 12,
|
||||
TileImageEXT = 4172,
|
||||
NodePayloadAMDX = 5068,
|
||||
NodeOutputPayloadAMDX = 5076,
|
||||
CallableDataNV = 5328,
|
||||
CallableDataKHR = 5328,
|
||||
IncomingCallableDataNV = 5329,
|
||||
@@ -636,6 +660,8 @@ enum class ImageChannelDataType : uint32_t
|
||||
Float = 14,
|
||||
UnormInt24 = 15,
|
||||
UnormInt101010_2 = 16,
|
||||
UnsignedIntRaw10EXT = 19,
|
||||
UnsignedIntRaw12EXT = 20,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
@@ -708,6 +734,16 @@ enum class AccessQualifier : uint32_t
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
enum class HostAccessQualifier : uint32_t
|
||||
{
|
||||
NoneINTEL = 0,
|
||||
ReadINTEL = 1,
|
||||
WriteINTEL = 2,
|
||||
ReadWriteINTEL = 3,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
enum class FunctionParameterAttribute : uint32_t
|
||||
{
|
||||
Zext = 0,
|
||||
@@ -776,7 +812,12 @@ enum class Decoration : uint32_t
|
||||
NoUnsignedWrap = 4470,
|
||||
WeightTextureQCOM = 4487,
|
||||
BlockMatchTextureQCOM = 4488,
|
||||
BlockMatchSamplerQCOM = 4499,
|
||||
ExplicitInterpAMD = 4999,
|
||||
NodeSharesPayloadLimitsWithAMDX = 5019,
|
||||
NodeMaxPayloadsAMDX = 5020,
|
||||
TrackFinishWritingAMDX = 5078,
|
||||
PayloadNodeNameAMDX = 5091,
|
||||
OverrideCoverageNV = 5248,
|
||||
PassthroughNV = 5250,
|
||||
ViewportRelativeNV = 5252,
|
||||
@@ -826,6 +867,9 @@ enum class Decoration : uint32_t
|
||||
MergeINTEL = 5834,
|
||||
BankBitsINTEL = 5835,
|
||||
ForcePow2DepthINTEL = 5836,
|
||||
StridesizeINTEL = 5883,
|
||||
WordsizeINTEL = 5884,
|
||||
TrueDualPortINTEL = 5885,
|
||||
BurstCoalesceINTEL = 5899,
|
||||
CacheSizeINTEL = 5900,
|
||||
DontStaticallyCoalesceINTEL = 5901,
|
||||
@@ -844,6 +888,8 @@ enum class Decoration : uint32_t
|
||||
SingleElementVectorINTEL = 6085,
|
||||
VectorComputeCallableFunctionINTEL = 6087,
|
||||
MediaBlockIOINTEL = 6140,
|
||||
StallFreeINTEL = 6151,
|
||||
FPMaxErrorDecorationINTEL = 6170,
|
||||
LatencyControlLabelINTEL = 6172,
|
||||
LatencyControlConstraintINTEL = 6173,
|
||||
ConduitKernelArgumentINTEL = 6175,
|
||||
@@ -855,6 +901,11 @@ enum class Decoration : uint32_t
|
||||
MMHostInterfaceMaxBurstINTEL = 6181,
|
||||
MMHostInterfaceWaitRequestINTEL = 6182,
|
||||
StableKernelArgumentINTEL = 6183,
|
||||
HostAccessINTEL = 6188,
|
||||
InitModeINTEL = 6190,
|
||||
ImplementInRegisterMapINTEL = 6191,
|
||||
CacheControlLoadINTEL = 6442,
|
||||
CacheControlStoreINTEL = 6443,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
@@ -932,6 +983,8 @@ enum class BuiltIn : uint32_t
|
||||
BaryCoordSmoothSampleAMD = 4997,
|
||||
BaryCoordPullModelAMD = 4998,
|
||||
FragStencilRefEXT = 5014,
|
||||
CoalescedInputCountAMDX = 5021,
|
||||
ShaderIndexAMDX = 5073,
|
||||
ViewportMaskNV = 5253,
|
||||
SecondaryPositionNV = 5257,
|
||||
SecondaryViewportMaskNV = 5258,
|
||||
@@ -985,6 +1038,8 @@ enum class BuiltIn : uint32_t
|
||||
HitKindKHR = 5333,
|
||||
CurrentRayTimeNV = 5334,
|
||||
HitTriangleVertexPositionsKHR = 5335,
|
||||
HitMicroTriangleVertexPositionsNV = 5337,
|
||||
HitMicroTriangleVertexBarycentricsNV = 5344,
|
||||
IncomingRayFlagsNV = 5351,
|
||||
IncomingRayFlagsKHR = 5351,
|
||||
RayGeometryIndexKHR = 5352,
|
||||
@@ -992,6 +1047,8 @@ enum class BuiltIn : uint32_t
|
||||
SMCountNV = 5375,
|
||||
WarpIDNV = 5376,
|
||||
SMIDNV = 5377,
|
||||
HitKindFrontFacingMicroTriangleNV = 5405,
|
||||
HitKindBackFacingMicroTriangleNV = 5406,
|
||||
CullMaskKHR = 6021,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
@@ -1143,6 +1200,7 @@ enum class Capability : uint32_t
|
||||
TextureSampleWeightedQCOM = 4484,
|
||||
TextureBoxFilterQCOM = 4485,
|
||||
TextureBlockMatchQCOM = 4486,
|
||||
TextureBlockMatch2QCOM = 4498,
|
||||
Float16ImageAMD = 5008,
|
||||
ImageGatherBiasLodAMD = 5009,
|
||||
FragmentMaskAMD = 5010,
|
||||
@@ -1150,6 +1208,8 @@ enum class Capability : uint32_t
|
||||
ImageReadWriteLodAMD = 5015,
|
||||
Int64ImageEXT = 5016,
|
||||
ShaderClockKHR = 5055,
|
||||
ShaderEnqueueAMDX = 5067,
|
||||
QuadControlKHR = 5087,
|
||||
SampleMaskOverrideCoverageNV = 5249,
|
||||
GeometryShaderPassthroughNV = 5251,
|
||||
ShaderViewportIndexLayerEXT = 5254,
|
||||
@@ -1209,10 +1269,13 @@ enum class Capability : uint32_t
|
||||
FragmentShaderPixelInterlockEXT = 5378,
|
||||
DemoteToHelperInvocation = 5379,
|
||||
DemoteToHelperInvocationEXT = 5379,
|
||||
DisplacementMicromapNV = 5380,
|
||||
RayTracingOpacityMicromapEXT = 5381,
|
||||
ShaderInvocationReorderNV = 5383,
|
||||
BindlessTextureNV = 5390,
|
||||
RayQueryPositionFetchKHR = 5391,
|
||||
AtomicFloat16VectorNV = 5404,
|
||||
RayTracingDisplacementMicromapNV = 5409,
|
||||
SubgroupShuffleINTEL = 5568,
|
||||
SubgroupBufferBlockIOINTEL = 5569,
|
||||
SubgroupImageBlockIOINTEL = 5570,
|
||||
@@ -1264,20 +1327,29 @@ enum class Capability : uint32_t
|
||||
DotProduct = 6019,
|
||||
DotProductKHR = 6019,
|
||||
RayCullMaskKHR = 6020,
|
||||
CooperativeMatrixKHR = 6022,
|
||||
BitInstructions = 6025,
|
||||
GroupNonUniformRotateKHR = 6026,
|
||||
FloatControls2 = 6029,
|
||||
AtomicFloat32AddEXT = 6033,
|
||||
AtomicFloat64AddEXT = 6034,
|
||||
LongConstantCompositeINTEL = 6089,
|
||||
LongCompositesINTEL = 6089,
|
||||
OptNoneINTEL = 6094,
|
||||
AtomicFloat16AddEXT = 6095,
|
||||
DebugInfoModuleINTEL = 6114,
|
||||
BFloat16ConversionINTEL = 6115,
|
||||
SplitBarrierINTEL = 6141,
|
||||
FPGAClusterAttributesV2INTEL = 6150,
|
||||
FPGAKernelAttributesv2INTEL = 6161,
|
||||
FPMaxErrorINTEL = 6169,
|
||||
FPGALatencyControlINTEL = 6171,
|
||||
FPGAArgumentInterfacesINTEL = 6174,
|
||||
GlobalVariableHostAccessINTEL = 6187,
|
||||
GlobalVariableFPGADecorationsINTEL = 6189,
|
||||
GroupUniformArithmeticKHR = 6400,
|
||||
MaskedGatherScatterINTEL = 6427,
|
||||
CacheControlsINTEL = 6441,
|
||||
RegisterLimitsINTEL = 6460,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
@@ -1315,6 +1387,73 @@ enum class PackedVectorFormat : uint32_t
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
enum class CooperativeMatrixOperands : uint32_t
|
||||
{
|
||||
NoneKHR = 0x0000,
|
||||
MatrixASignedComponentsKHR = 0x0001,
|
||||
MatrixBSignedComponentsKHR = 0x0002,
|
||||
MatrixCSignedComponentsKHR = 0x0004,
|
||||
MatrixResultSignedComponentsKHR = 0x0008,
|
||||
SaturatingAccumulationKHR = 0x0010,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
BITMASK_OPERATORS(CooperativeMatrixOperands);
|
||||
|
||||
enum class CooperativeMatrixLayout : uint32_t
|
||||
{
|
||||
RowMajorKHR = 0,
|
||||
ColumnMajorKHR = 1,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
enum class CooperativeMatrixUse : uint32_t
|
||||
{
|
||||
MatrixAKHR = 0,
|
||||
MatrixBKHR = 1,
|
||||
MatrixAccumulatorKHR = 2,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
enum class InitializationModeQualifier : uint32_t
|
||||
{
|
||||
InitOnDeviceReprogramINTEL = 0,
|
||||
InitOnDeviceResetINTEL = 1,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
enum class LoadCacheControl : uint32_t
|
||||
{
|
||||
UncachedINTEL = 0,
|
||||
CachedINTEL = 1,
|
||||
StreamingINTEL = 2,
|
||||
InvalidateAfterReadINTEL = 3,
|
||||
ConstCachedINTEL = 4,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
enum class StoreCacheControl : uint32_t
|
||||
{
|
||||
UncachedINTEL = 0,
|
||||
WriteThroughINTEL = 1,
|
||||
WriteBackINTEL = 2,
|
||||
StreamingINTEL = 3,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
enum class NamedMaximumNumberOfRegisters : uint32_t
|
||||
{
|
||||
AutoINTEL = 0,
|
||||
Max,
|
||||
Invalid = ~0U,
|
||||
};
|
||||
|
||||
using IdResultType = Id;
|
||||
|
||||
using IdResult = Id;
|
||||
@@ -1525,6 +1664,20 @@ struct LocalSizeHintIdParams
|
||||
Id zsizehint;
|
||||
};
|
||||
|
||||
struct StaticNumWorkgroupsAMDXParams
|
||||
{
|
||||
Id xsize;
|
||||
Id ysize;
|
||||
Id zsize;
|
||||
};
|
||||
|
||||
struct MaxNumWorkgroupsAMDXParams
|
||||
{
|
||||
Id xsize;
|
||||
Id ysize;
|
||||
Id zsize;
|
||||
};
|
||||
|
||||
struct MaxWorkgroupSizeINTELParams
|
||||
{
|
||||
uint32_t max_x_size;
|
||||
@@ -1532,6 +1685,12 @@ struct MaxWorkgroupSizeINTELParams
|
||||
uint32_t max_z_size;
|
||||
};
|
||||
|
||||
struct FPFastMathDefaultParams
|
||||
{
|
||||
Id targetType;
|
||||
Id fastMathMode;
|
||||
};
|
||||
|
||||
struct ExecutionModeAndParamData
|
||||
{
|
||||
ExecutionModeAndParamData(ExecutionMode v = ExecutionMode::Invalid) : value(v) {}
|
||||
@@ -1553,6 +1712,10 @@ struct ExecutionModeAndParamData
|
||||
uint32_t signedZeroInfNanPreserve;
|
||||
uint32_t roundingModeRTE;
|
||||
uint32_t roundingModeRTZ;
|
||||
Id maxNodeRecursionAMDX;
|
||||
StaticNumWorkgroupsAMDXParams staticNumWorkgroupsAMDX;
|
||||
Id shaderIndexAMDX;
|
||||
MaxNumWorkgroupsAMDXParams maxNumWorkgroupsAMDX;
|
||||
uint32_t outputPrimitivesNV;
|
||||
uint32_t outputPrimitivesEXT;
|
||||
uint32_t sharedLocalMemorySizeINTEL;
|
||||
@@ -1564,9 +1727,13 @@ struct ExecutionModeAndParamData
|
||||
uint32_t maxWorkDimINTEL;
|
||||
uint32_t numSIMDWorkitemsINTEL;
|
||||
uint32_t schedulerTargetFmaxMhzINTEL;
|
||||
FPFastMathDefaultParams fPFastMathDefault;
|
||||
uint32_t streamingInterfaceINTEL;
|
||||
uint32_t registerMapInterfaceINTEL;
|
||||
uint32_t namedBarrierCountINTEL;
|
||||
uint32_t maximumRegistersINTEL;
|
||||
Id maximumRegistersIdINTEL;
|
||||
NamedMaximumNumberOfRegisters namedMaximumRegistersINTEL;
|
||||
};
|
||||
|
||||
operator ExecutionMode() const { return value; }
|
||||
@@ -1604,6 +1771,18 @@ struct LatencyControlConstraintINTELParams
|
||||
uint32_t relativeCycle;
|
||||
};
|
||||
|
||||
struct CacheControlLoadINTELParams
|
||||
{
|
||||
uint32_t cacheLevel;
|
||||
LoadCacheControl cacheControl;
|
||||
};
|
||||
|
||||
struct CacheControlStoreINTELParams
|
||||
{
|
||||
uint32_t cacheLevel;
|
||||
StoreCacheControl cacheControl;
|
||||
};
|
||||
|
||||
struct DecorationAndParamData
|
||||
{
|
||||
DecorationAndParamData(Decoration v = Decoration::Invalid) : value(v) {}
|
||||
@@ -1632,6 +1811,8 @@ struct DecorationAndParamData
|
||||
uint32_t maxByteOffset;
|
||||
Id alignmentId;
|
||||
Id maxByteOffsetId;
|
||||
Id nodeSharesPayloadLimitsWithAMDX;
|
||||
Id nodeMaxPayloadsAMDX;
|
||||
uint32_t secondaryViewportRelativeNV;
|
||||
uint32_t sIMTCallINTEL;
|
||||
uint32_t funcParamIOKindINTEL;
|
||||
@@ -1646,6 +1827,8 @@ struct DecorationAndParamData
|
||||
uint32_t maxReplicatesINTEL;
|
||||
uint32_t bankBitsINTEL;
|
||||
uint32_t forcePow2DepthINTEL;
|
||||
uint32_t stridesizeINTEL;
|
||||
uint32_t wordsizeINTEL;
|
||||
uint32_t cacheSizeINTEL;
|
||||
uint32_t prefetchINTEL;
|
||||
MathOpDSPModeINTELParams mathOpDSPModeINTEL;
|
||||
@@ -1657,6 +1840,7 @@ struct DecorationAndParamData
|
||||
uint32_t bufferLocationINTEL;
|
||||
uint32_t iOPipeStorageINTEL;
|
||||
FunctionFloatingPointModeINTELParams functionFloatingPointModeINTEL;
|
||||
float fPMaxErrorDecorationINTEL;
|
||||
uint32_t latencyControlLabelINTEL;
|
||||
LatencyControlConstraintINTELParams latencyControlConstraintINTEL;
|
||||
uint32_t mMHostInterfaceAddressWidthINTEL;
|
||||
@@ -1665,6 +1849,10 @@ struct DecorationAndParamData
|
||||
AccessQualifier mMHostInterfaceReadWriteModeINTEL;
|
||||
uint32_t mMHostInterfaceMaxBurstINTEL;
|
||||
uint32_t mMHostInterfaceWaitRequestINTEL;
|
||||
InitializationModeQualifier initModeINTEL;
|
||||
uint32_t implementInRegisterMapINTEL;
|
||||
CacheControlLoadINTELParams cacheControlLoadINTEL;
|
||||
CacheControlStoreINTELParams cacheControlStoreINTEL;
|
||||
};
|
||||
|
||||
operator Decoration() const { return value; }
|
||||
@@ -2045,6 +2233,11 @@ enum class Op : uint16_t
|
||||
UDotAccSatKHR = 4454,
|
||||
SUDotAccSat = 4455,
|
||||
SUDotAccSatKHR = 4455,
|
||||
TypeCooperativeMatrixKHR = 4456,
|
||||
CooperativeMatrixLoadKHR = 4457,
|
||||
CooperativeMatrixStoreKHR = 4458,
|
||||
CooperativeMatrixMulAddKHR = 4459,
|
||||
CooperativeMatrixLengthKHR = 4460,
|
||||
TypeRayQueryKHR = 4472,
|
||||
RayQueryInitializeKHR = 4473,
|
||||
RayQueryTerminateKHR = 4474,
|
||||
@@ -2056,6 +2249,10 @@ enum class Op : uint16_t
|
||||
ImageBoxFilterQCOM = 4481,
|
||||
ImageBlockMatchSSDQCOM = 4482,
|
||||
ImageBlockMatchSADQCOM = 4483,
|
||||
ImageBlockMatchWindowSSDQCOM = 4500,
|
||||
ImageBlockMatchWindowSADQCOM = 4501,
|
||||
ImageBlockMatchGatherSSDQCOM = 4502,
|
||||
ImageBlockMatchGatherSADQCOM = 4503,
|
||||
GroupIAddNonUniformAMD = 5000,
|
||||
GroupFAddNonUniformAMD = 5001,
|
||||
GroupFMinNonUniformAMD = 5002,
|
||||
@@ -2067,6 +2264,11 @@ enum class Op : uint16_t
|
||||
FragmentMaskFetchAMD = 5011,
|
||||
FragmentFetchAMD = 5012,
|
||||
ReadClockKHR = 5056,
|
||||
FinalizeNodePayloadsAMDX = 5075,
|
||||
FinishWritingNodePayloadAMDX = 5078,
|
||||
InitializeNodePayloadsAMDX = 5090,
|
||||
GroupNonUniformQuadAllKHR = 5110,
|
||||
GroupNonUniformQuadAnyKHR = 5111,
|
||||
HitObjectRecordHitMotionNV = 5249,
|
||||
HitObjectRecordHitWithIndexMotionNV = 5250,
|
||||
HitObjectRecordMissMotionNV = 5251,
|
||||
@@ -2105,6 +2307,8 @@ enum class Op : uint16_t
|
||||
SetMeshOutputsEXT = 5295,
|
||||
GroupNonUniformPartitionNV = 5296,
|
||||
WritePackedPrimitiveIndices4x8NV = 5299,
|
||||
FetchMicroTriangleVertexPositionNV = 5300,
|
||||
FetchMicroTriangleVertexBarycentricNV = 5301,
|
||||
ReportIntersectionNV = 5334,
|
||||
ReportIntersectionKHR = 5334,
|
||||
IgnoreIntersectionNV = 5335,
|
||||
@@ -2191,6 +2395,7 @@ enum class Op : uint16_t
|
||||
TypeStructContinuedINTEL = 6090,
|
||||
ConstantCompositeContinuedINTEL = 6091,
|
||||
SpecConstantCompositeContinuedINTEL = 6092,
|
||||
CompositeConstructContinuedINTEL = 6096,
|
||||
ConvertFToBF16INTEL = 6116,
|
||||
ConvertBF16ToFINTEL = 6117,
|
||||
ControlBarrierArriveINTEL = 6142,
|
||||
@@ -2203,6 +2408,8 @@ enum class Op : uint16_t
|
||||
GroupLogicalAndKHR = 6406,
|
||||
GroupLogicalOrKHR = 6407,
|
||||
GroupLogicalXorKHR = 6408,
|
||||
MaskedGatherINTEL = 6428,
|
||||
MaskedScatterINTEL = 6429,
|
||||
|
||||
Max,
|
||||
};
|
||||
@@ -2381,6 +2588,7 @@ DECLARE_STRINGISE_TYPE(rdcspv::FPOperationMode);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::OverflowModes);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::LinkageType);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::AccessQualifier);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::HostAccessQualifier);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::FunctionParameterAttribute);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::Decoration);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::BuiltIn);
|
||||
@@ -2392,3 +2600,10 @@ DECLARE_STRINGISE_TYPE(rdcspv::RayQueryIntersection);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::RayQueryCommittedIntersectionType);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::RayQueryCandidateIntersectionType);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::PackedVectorFormat);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::CooperativeMatrixOperands);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::CooperativeMatrixLayout);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::CooperativeMatrixUse);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::InitializationModeQualifier);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::LoadCacheControl);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::StoreCacheControl);
|
||||
DECLARE_STRINGISE_TYPE(rdcspv::NamedMaximumNumberOfRegisters);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -954,6 +954,7 @@ void Reflector::MakeReflection(const GraphicsAPI sourceAPI, const ShaderStage st
|
||||
case SourceLanguage::ESSL:
|
||||
case SourceLanguage::GLSL: reflection.debugInfo.encoding = ShaderEncoding::GLSL; break;
|
||||
case SourceLanguage::HLSL: reflection.debugInfo.encoding = ShaderEncoding::HLSL; break;
|
||||
case SourceLanguage::Slang: reflection.debugInfo.encoding = ShaderEncoding::HLSL; break;
|
||||
case SourceLanguage::OpenCL_C:
|
||||
case SourceLanguage::OpenCL_CPP:
|
||||
case SourceLanguage::CPP_for_OpenCL:
|
||||
@@ -961,6 +962,9 @@ void Reflector::MakeReflection(const GraphicsAPI sourceAPI, const ShaderStage st
|
||||
case SourceLanguage::Invalid:
|
||||
case SourceLanguage::SYCL:
|
||||
case SourceLanguage::HERO_C:
|
||||
case SourceLanguage::NZSL:
|
||||
case SourceLanguage::WGSL:
|
||||
case SourceLanguage::Zig:
|
||||
case SourceLanguage::Max: break;
|
||||
}
|
||||
|
||||
@@ -2309,6 +2313,34 @@ void Reflector::AddSignatureParameter(const bool isInput, const ShaderStage stag
|
||||
#include "data/glsl_shaders.h"
|
||||
#include "glslang_compile.h"
|
||||
|
||||
#if 1
|
||||
|
||||
TEST_CASE("DO NOT COMMIT - convenience test", "[spirv]")
|
||||
{
|
||||
// this test loads a file from disk and passes it through DXBC::DXBCContainer. Useful for when you
|
||||
// are iterating on a shader and don't want to have to load a whole capture.
|
||||
rdcarray<uint32_t> spirv;
|
||||
FileIO::ReadAll("T:/tmp/a.spv", spirv);
|
||||
|
||||
rdcspv::Reflector spv;
|
||||
spv.Parse(spirv);
|
||||
|
||||
rdcstr entryPoint = spv.EntryPoints()[0].name;
|
||||
ShaderStage stage = spv.EntryPoints()[0].stage;
|
||||
|
||||
ShaderReflection refl;
|
||||
ShaderBindpointMapping mapping;
|
||||
SPIRVPatchData patchData;
|
||||
spv.MakeReflection(GraphicsAPI::Vulkan, stage, entryPoint, {}, refl, mapping, patchData);
|
||||
|
||||
std::map<size_t, uint32_t> instructionLines;
|
||||
rdcstr disasm = spv.Disassemble(entryPoint, instructionLines);
|
||||
|
||||
RDCLOG("%s", disasm.c_str());
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
TEST_CASE("Validate SPIR-V reflection", "[spirv][reflection]")
|
||||
{
|
||||
ShaderType type = ShaderType::Vulkan;
|
||||
|
||||
Reference in New Issue
Block a user