13ccbe2b84
RD DXIL Disassembly: decode "dx.op.textureStore"
...
Example Output
call void @dx.op.textureStore.f32(i32 67, %dx.types.Handle %OutLuma_UAV_2d, i32 %1, i32 %2, i32 undef, float %18, float %18, float %18, float %18, i8 15)
Becomes
OutLuma[_1, _2] = {_18, _18, _18, _18};
2024-05-02 07:09:49 +01:00
d1150f244f
RD DXIL Disassembly: decode "dx.op.textureLoad"
...
Example Output
%TextureLoad = call %dx.types.ResRet.f32 @dx.op.textureLoad.f32(i32 66, %dx.types.Handle %texSSAO_texture_2d, i32 0, i32 %23, i32 %24, i32 undef, i32 undef, i32 undef, i32 undef)
Becomes
_dx.types.ResRet.f32 _TextureLoad = texSSAO.Load(_23, _24);
2024-05-02 07:09:43 +01:00
e6bf418c30
RD DXIL Disassembly: decode "dx.op.bufferStore" &"dx.op.rawBufferStore"
...
Example Output
call void @dx.op.rawBufferStore.f32(i32 140, %dx.types.Handle %Exposure_UAV_structbuf, i32 1, i32 0, float %75, float undef, float undef, float undef, i8 1, i32 4)
call void @dx.op.rawBufferStore.f32(i32 140, %dx.types.Handle %Exposure_UAV_structbuf, i32 2, i32 0, float %FMin, float undef, float undef, float undef, i8 1, i32 4)
call void @dx.op.rawBufferStore.f32(i32 140, %dx.types.Handle %Exposure_UAV_structbuf, i32 3, i32 0, float %59, float undef, float undef, float undef, i8 1, i32 4)
Becomes
Exposure[1] = {_75};
Exposure[2] = {_FMin};
Exposure[3] = {_59};
2024-05-02 07:09:38 +01:00
30cf5412ba
RD DXIL Disassembly: decode "dx.op.bufferLoad" &"dx.op.rawBufferLoad"
...
Example Output
%31 = call %dx.types.ResRet.i32 @dx.op.bufferLoad.i32(i32 68, %dx.types.Handle %bufOut_UAV_structbuf, i32 1, i32 0);
Becomes
_dx.types.ResRet.i32 _31 = bufOut[1];
2024-05-01 15:58:04 +01:00
70c5fd91ad
RD DXIL Disassembly: handle non-constant args during specifc decoding
...
dx.op.loadInput
dx.op.storeOutput
dx.op.createHandle
dx.op.cbufferLoad
dx.op.cbufferLoadLegacy
2024-05-01 14:52:46 +01:00
99e10f24c7
RD DXIL Disassembly: decode "dx.op.cbufferLoad*" to show members
...
CBuffer[0] blah Space: 0 Reg: 0 Count: 1
{
int4 mult;
};
Example Output
_dx.types.CBufRet.i32 %1 = CBufferLoadLegacy(%blah_cbuffer, 0);
becomes
_dx.types.CBufRet.i32 _1 = {blah.mult};
2024-05-01 14:52:46 +01:00
9b97fa5ed0
RD DXIL Disassembly: improve presentation of Inputs and Outputs
...
Handle Inputs and Outputs which have multiple rows
Prefix Inputs with "<IN>."
Prefix Outputs with "<OUT>."
Inputs and Outputs can share the same names (semantic names) i.e. COLOR, INTERPOLATOR
2024-05-01 10:26:14 +01:00
18b655edf5
RD DXIL Disassembly refactoring
...
Renamed:
DXIL::EntryPoint -> DXIL::EntryPointInterface
DXIL::Program::FetchEntryPoints() -> DXIL::Program::FetchEntryPointInterfaces()
Deleted EntryPointsInfo helper struct
2024-05-01 08:07:27 +01:00
4d10322908
RD DXIL Disassembly: decode "dx.op.createHandle" to show resource name
2024-05-01 08:05:29 +01:00
01519c7b49
OpDebugValue handling improve offset for nested complex types
...
Use member offset data from DebugTypeComposite for member offsets
Use type dimensions to compute offset for children
Propagate the parent offset as a base for the children to offset from
2024-05-01 07:45:11 +01:00
3852d21aa5
OpDebugValue handling added asserts to catch invalid indexes
2024-05-01 07:45:11 +01:00
dc8c758a55
Dynamically allocate BC7 data only when needed
2024-04-30 18:28:33 +01:00
0dfb8474c1
Re-use ray dispatch patching on replay
2024-04-30 18:28:33 +01:00
ffb9c6cb3b
Rebase associations after patching state object desc
2024-04-30 18:28:33 +01:00
b06e7030a5
Implement GPU unwrapping of handles in shader records
2024-04-30 18:28:33 +01:00
a9849c050b
Implement shader identifier patching during capture
2024-04-30 18:28:33 +01:00
cfc5204a69
Don't require dxc for compiling RT patching shaders
...
* We do some manual uint64 emulation with uint2 which compiles on fxc, re-used
from the execute indirect patching.
2024-04-30 18:28:33 +01:00
c26c4b11d0
Set up a patching function to unwrap shader records during capture
2024-04-30 18:28:33 +01:00
db44d06d41
Manage internal GPU buffers as refcounted objects on D3D12
...
* This will enable sharing of these buffers more easily when there are multiple
lifetimes that are more difficult to co-ordinate.
2024-04-30 18:28:33 +01:00
34aba75128
Register local root signatures and databases of state object exports
...
* This information will be used for wrapping, unwrapping & replay-remapping of
shader records
2024-04-30 18:28:33 +01:00
4c3de55d20
Dynamic rendering can be started in any command buffer
2024-04-30 10:40:39 +01:00
47c5773d08
Fix crash in vulkan pipeline state viewer
2024-04-30 09:50:34 +01:00
d0e3d9ce6d
Vulkan AS descriptor and SPIR-V changes
...
Also has change where the AS is tracked in command buffers so that we know when it has been built - unbuilt ASes are skipped before serialisation.
2024-04-29 11:46:56 +01:00
6de42041e6
Remove compile option "-mfpu=neon-vfpv" on arm64 processors
...
The compile option is set for file "rdparty/stb/stb_impl.c".
Apple Silicon is an arm64 processor and the compile option was not valid.
2024-04-27 11:58:44 +01:00
f076105548
Add missing docstrings for ShaderStageMask
2024-04-26 14:43:31 +01:00
aa419f851b
Don't pass rdcstr through to logging directly
2024-04-26 14:36:18 +01:00
aa4f8fe62b
Update SPIR-V references to NV opcodes
2024-04-26 14:25:45 +01:00
ce7a23b611
Prefer KHR to NV for opcode aliases when making SPIR-V helpers
2024-04-26 13:55:19 +01:00
c098971f79
Serialise ray pipeline binding and dispatching as-is
...
* This does not contain patching of shader records so currently the ray dispatch
is not replayed
2024-04-26 13:55:19 +01:00
caa6ba3dd1
Remove an old and redundant feature check
2024-04-26 13:55:19 +01:00
e3e191f8d6
Wrap and serialise state objects as pass-through
2024-04-26 13:55:19 +01:00
7e7bbf58a8
Reflect multiple entry points & ray properties from DXIL shaders
2024-04-26 13:55:19 +01:00
476fed06d6
Add function to enumerate the entry points in a given shader
2024-04-26 13:55:19 +01:00
89bea3ea8b
Add new shader enums for RT shader stages
2024-04-26 13:55:18 +01:00
5366ce7b4a
RD DXIL Disassembly: ignore "undef" parameters in "dx.op" functions
2024-04-26 08:18:20 +01:00
756a980d96
RD DXIL Disassembly: ignore first getelemenptr index if it is zero
...
Before
GroupShared float* _30 = shared_pos[0] + _29;
After
GroupShared float* _30 = shared_pos[_29];
2024-04-26 06:18:16 +01:00
b8f77d8393
RD DXIL Disassembly: EntryPoint Resources output
...
Includes EntryPoint Resources parsing
Includes handling column index for inputs/outputs access
2024-04-25 18:42:20 +01:00
b8621e81d5
Add SignatureElement constants used when parsing DXIL Signatures
2024-04-24 13:37:51 +01:00
6a329ba5b3
RD DXIL Disassembly: display DX parameter names as inline comment
2024-04-24 09:33:21 +01:00
8b534e8f18
Demos: Fix validation errors in D3D12_Compute_Only
2024-04-24 09:02:32 +01:00
ec9517c43a
RD DXIL Disassembly: show dx parameter names on dx.op function calls
...
The parameter names extracted from the dx function signatures
2024-04-24 07:49:06 +01:00
2b59d21fd9
RD DXIL Disassembly: change getelementptr output
...
Convert the DXIL addrspace value into string
Hand de-mangle pointer name
DXC:
%3 = getelementptr [6 x float], [6 x float] addrspace(3)* @"\01?s_x@@3@$$A.1dim", i32 0, i32 %9
RD:
GroupShared float* _3 = s_x[0] + _9;
2024-04-24 07:01:31 +01:00
601dc58a52
RD DXIL Disassembly: change "br" output
...
if (_32) goto _132 else goto _33;
or
goto _132;
2024-04-23 13:33:16 +01:00
007f4d46f4
RD DXIL Disassembly: change "load" and "store" output
...
load
float _49 = *_48; // align 4
store
*_30 = _27; // align 4
2024-04-23 13:33:10 +01:00
248a2383ed
RD DXIL Disassembly: convert "select" to C-style ? operator
2024-04-23 11:23:24 +01:00
bdc0a0bc2d
RD DXIL Disassembly: explicit handling for specific FP comparisons
...
FOrdFalse
FOrdTrue
FOrd
FUnord
2024-04-23 11:23:20 +01:00
9bb9c4ba6e
RD DXIL Disassembly: use C-style operators and function names
...
Use C-style operators and function names as much as possible to replace comparison, arithmetic, casting instructions
2024-04-23 10:28:01 +01:00
0f2c7490ce
RD DXIL Disassembly: display function name instead of full signature
...
Divide up "funcSigs" array into "name" and "signature" arrays
2024-04-23 07:10:14 +01:00
53e76cfa86
RD DXIL Disassembly: do not show Op flags string
2024-04-23 07:10:08 +01:00
f27659e902
RD DXIL disassebmly: do not show types on parameters
2024-04-23 07:10:03 +01:00
Jake Turner