Commit Graph

11232 Commits

Author SHA1 Message Date
Jake Turner b53bd38828 Use correct nextInstruction value when generating callstack for inlines 2025-05-14 13:45:51 +01:00
baldurk b19c5b9f73 Prevent crash if programmatic capture happens after deleting swapchain 2025-05-13 15:16:42 +01:00
baldurk 2665c1f65c Add decoding of V2 pix markers 2025-05-13 14:11:42 +01:00
baldurk 71e607cf0e Use internal printf for decoding PIX event formats. Closes #3607
* The internal printf was already used for all numeric types but PIX of course
  has special encoding for strings so this was manually handled. Instead use the
  callback-based formatter and decode strings for there, so that varargs string
  length and string padding formatters are supported.
2025-05-13 14:11:42 +01:00
baldurk fc9999d67c Add support for varargs length in utf8 printf 2025-05-13 14:11:42 +01:00
zllangty 9fab650555 Add LoongArch64 support
With addition macros project able to build and run on LoongArch64 machine
2025-05-13 12:18:06 +01:00
Jake Turner 0e2cfde411 D3D11 GroupShared simulation changes
* On the active thread GSM reads come from the local GSM cache (not the global GSM data)
* This brings consistency in debugger UI when seeing the GSM data as variables (which is populated from the local GSM cache) and seeing the results of reading from the GSM data

GSM writes already populated the local GSM cache and the global GSM data
GSM Sync populates the local GSM cache with the data from the global GSM data
2025-05-10 12:00:05 +01:00
Jake Turner 3408a3be86 Null out "before" change completely not just clear the name 2025-05-08 16:08:25 +01:00
Jake Turner 1598abfa3b Manually record ShaderVariableChange's for Load/Store/Atomic operations 2025-05-08 16:06:35 +01:00
Jake Turner 28a5ae4b01 Do not record ShaderVariableChanges or any results from DXC nop's 2025-05-08 16:06:35 +01:00
Jake Turner 4940451e4b Make sure all SSA lifetimes extend to a uniform block (not a loop block)
* Update any SSA max points which are inside a loop to the next uniform block
* This covers the case of SSA IDs that are assigned to but never accessed
2025-05-08 16:06:35 +01:00
Jake Turner a55884043a Simplify MarkResourceAccess() to give consistent ShaderVariableChange 2025-05-08 16:06:35 +01:00
Jake Turner 41eb7483cc Match disassembly SSA ID names for annotated resource handles 2025-05-08 10:25:00 +01:00
Jake Turner 5169d808bc DXIL Debugger support for partial convergence blocks
Example HLSL construct that is correct after this change (and incorrect before this change)

if (id >= 2 && id <= 20)
{
...
}
else
{
... <THE CORRECT THREADS MERGE HERE INTO A SINGLE TANGLE>
}
2025-05-07 12:17:18 +01:00
Jake Turner ecc4fcc8d5 DXIL ControlFlow support for generating points of partial convergence
Also tweaked DXIL ControlFlow GraphVis output

Generate the graph in a string for use with RDCLOG or writing to a file
Changed (full) convergence nodes to be blue rectangles
Partial convergence nodes are rounded green rectangles
Partial convergence edges are green dashed lines

FIXUP GENERATE PARTIAL CONVERGENCE
2025-05-07 12:16:37 +01:00
Jake Turner a6f47d3061 Shader ControlFlow only add new merge points
Previously it would only test against the head of the existing merge points, now checks the whole array
2025-05-07 12:15:24 +01:00
Jake Turner bd2061c21c Fix DXBC Debugger writes to GSM structured data 2025-05-07 11:56:25 +01:00
Jake Turner 7d35635844 Only default activate lane zero for SPIRV single threaded compute debug
Workgroup and Subgroup compute debug will set lane Active/SubgroupId properties for all threads
2025-05-07 11:15:05 +01:00
Jake Turner 79e80c8337 Added assert for Op::ControlBarrier that the workgroup is converged
New helper method ThreadState::WorkgroupIsDiverged()
2025-05-07 11:03:20 +01:00
baldurk 4dbcfca343 Fix reflection of structs containing 16-bit types. Closes #3605
* It is impossible to emit a true 16-bit type on fxc, the minXX types we round
  up internally to a 32-bit type since that's how they are defined to appear in
  external resources like cbuffers and SRV/UAVs.
* The new 16-bit type enums that are shared between fxc/dxc structs are not
  actually ever emitted by fxc for RDEF types.
2025-05-05 14:49:24 +01:00
baldurk 62be3340a5 Check more carefully if DX11 maps are intercepted properly. Closes #3603
* Maps are recorded as open whenever we intercept them, usually only falling off
  for high traffic resources or direct maps like WRITE_NO_OVERWRITE.
* Unmaps can be successful any time as long as they're intercepted as reads (no-
  op) or write discard (since we just need to intercept these).
* Unmaps from other write types require a map during an active capture to ensure
  we properly set up shadow pointers.
2025-05-05 12:42:28 +01:00
baldurk 2288237723 Early detect and error when launching reserved filenames for capture
* This is a safety measure to ensure we never add hooks to system processes, so
  we should detect this case earlier and error for the user.
2025-05-05 10:49:42 +01:00
Camden Mannett 7a551bcfc2 Add AS descriptor handling in vkCmdPushDescriptorSetKHR
Closes #3598
2025-05-03 15:45:49 +01:00
baldurk bb10ae25bb Bump version to v1.39 2025-05-02 15:07:38 +01:00
baldurk a8a14bc317 When possible reject aliased pdb names using HASH 2025-05-01 15:40:23 +01:00
baldurk f5506fcec3 Workaround of pixel history crash with depth-only UAV writes 2025-05-01 10:36:07 +01:00
Jake Turner df08881ef2 Add asserts to check for out of bounds GSM variable access 2025-04-30 11:59:03 +01:00
Jake Turner 35f91b2575 Compute GSM raw variable declaration element count from byte count 2025-04-30 11:59:03 +01:00
Jake Turner cf879397bd Fix incorrect indexing when getting GSM Register Index 2025-04-30 11:59:02 +01:00
Cam Mannett 47ee186e65 Retain initial contents type on softmem flush reset
Otherwise resources are filtered out before writing.

Change-Id: I76e096472aa3a8b32b81ccd4612da7330173ed47
2025-04-29 15:50:02 +01:00
baldurk 36e53ae0cd Ensure color format is always set for GL pixel history framebuffers 2025-04-29 12:09:51 +01:00
baldurk 8e86f79c72 Fix compiling pixel history shaders on GLES breaking 2025-04-29 12:09:38 +01:00
baldurk ade38c43d4 Only apply dynamic offsets for the relevant pipeline type 2025-04-24 16:12:15 +01:00
baldurk 5b5bec6334 Handle forward referenced function members in debuginfo types 2025-04-24 16:12:15 +01:00
Le Philousophe bf1ebeeb86 Allow custom visualisation shaders to be used with GLES
With GLES, a precision specifier is mandatory for float types.
Specifying one in the user shader is not enough because it happens too
late after uvec2 and uvec4 uses in the custom prefix.
2025-04-24 12:02:24 +01:00
baldurk e03ea6b040 Fix incorrect log print 2025-04-23 10:53:50 +01:00
baldurk 4dfedae094 Make sure that const pNext chains aren't modified during patching
* Even if we duplicate the base structure it is not safe to modify the const
  pNext chain without copying it too.
2025-04-23 10:53:50 +01:00
Jake Turner 498e767272 DXBC debugger clamp out of bounds component count to maximum of four 2025-04-22 12:38:27 +01:00
Jake Turner 4ead1e4423 Handle initialising a DXIL constant struct to NULL
It is a nop because ShaderVariable starts initialised to 0
2025-04-22 12:37:28 +01:00
Jake Turner 261f957d5b SPIRV workgroup debugger, add padding lanes to align to subgroup size 2025-04-18 13:58:10 +01:00
Jake Turner 5f00ed9d39 SPIRV Debugger workgroup debugging fixes
Set the thread property SubgroupId for the extra lanes outside of the subgroup
pass the workgroup laneIndex to BeginDebug
Set the thread property GroupThreadIndex, GroupFlatIndex for all workgroup lanes
2025-04-18 13:58:10 +01:00
Jake Turner c1fb809f17 SPIRV Debugger, add asserts to ensure the lane index is in range
Specifically when computing the active lanes from the activeMask array
2025-04-18 13:58:09 +01:00
Jake Turner f5222ed547 DXIL Debugger tweak subgroup active lanes helper
add asserts to ensure the lane index is in range
return the first lane in the subgroup
2025-04-18 13:58:09 +01:00
Jake Turner ede0c1d0ee D3D12 Workgroup debugger, add padding lanes to align to subgroup size 2025-04-18 13:58:09 +01:00
Jake Turner 53ad61b6a5 D3D12 Workgroup debugger, use SV_GroupThreadID for threadid
Use SV_GroupThreadID to fill in threadid in the compute fetcher instead of SV_DispatchThreadID
Keep SV_DispatchThreadID to identify the candidate thread
2025-04-18 13:58:09 +01:00
baldurk eb05d1b0a6 Fix forced references failing on ASs 2025-04-18 11:20:04 +01:00
baldurk 3b29508f2f Fix vulkan structured data conversion 2025-04-18 11:19:47 +01:00
baldurk e1dd947e1e work around compile error asserting on static const 2025-04-17 17:16:50 +01:00
baldurk 506d6c6d7b Fix self-capture for vulkan captures using ASs
* The problem here is that due to design flaws in the extension when ASs are in
  use we don't know whether a memory allocation will need BDA or not an the
  application doesn't have to set any flag - unlike for normal buffer BDA. So we
  promote (almost) all memory allocations to BDA when using ASs even if they're
  not needed.
* This normally works fine except if during self-capture the replay process
  allocates some normal memory before all application replayed allocations have
  been made, the self-capturing will promote it to BDA and request a replayable
  address that might clash with a later address the application had used and
  would be needed.
* To solve this, we ensure that during capture we don't create wrapped
  allocations more than necessary - to avoid causing clashes - as well as
  ensuring that on replay we only create new allocations after all replayed
  allocations.
* We also take advantage of dedicated allocations for fake swapchain images,
  since dedicated image allocations will not be promoted to BDA.
2025-04-17 16:21:19 +01:00
Martyn Jacques 84aa4c7fb6 Reset planar flag when remapping textures on vulkan replay 2025-04-17 16:20:21 +01:00